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am186 ? em and am188 ? em microcontrollers users manual
? 1997 advanced micro devices, inc. all rights reserved. advanced micro devices, inc. ("amd") reserves the right to make changes in its products without notice in order to improve design or performance characteristics. the information in this publication is believed to be accurate at the time of publication, but amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. amd disclaims responsibility for any consequences resulting from the use of the information included in this publication. this publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of merchantability or fitness for a particular purpose. amd products are not authorized for use as critical components in life support devices or systems without amds written approval. amd assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of amd products except as provided in amds terms and conditions of sale for such products. trademarks amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am386 and am486 are registered trademarks, and am186, am188, e86, amd facts-on-demand, and k86 are trademarks of advanced micro devices, inc. fusione86 is a service mark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
iii if you have questions, were here to help you. customer service the amd customer service network includes u.s. offices, international offices, and a customer training center. expert technical assistance is available from the worldwide staff of amd field application engineers and factory support staff to answer e86 ? family hardware and software development questions. hotline and world wide web support for answers to technical questions, amd provides a toll-free number for direct access to our corporate applications hotline. also available is the amd world wide web home page and ftp site, which provides the latest e86 family product information, including technical information and data on upcoming product releases. corporate applications hotline (800) 222-9323 toll-free for u.s. and canada 44-(0) 1276-803-299 u.k. and europe hotline world wide web home page and ftp site to access the amd home page, go to http://www.amd.com. to download documents and software, ftp to ftp.amd.com and log on as anonymous using your e-mail address as a password. or via your web browser, go to ftp://ftp.amd.com. questions, requests, and input concerning amds www pages can be sent via e-mail to webmaster@amd.com. documentation and literature free e86 family information such as data books, users manuals, data sheets, application notes, the fusione86 sm partner solutions catalog, and other literature is available with a simple phone call. internationally, contact your local amd sales office for complete e86 family literature. literature ordering 800-222-9323 toll-free for u.s. and canada 512-602-5651 direct dial worldwide 512-602-7639 fax 800-222-9323 amd facts-on-demand ? faxback service toll-free for u.s. and canada
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table of contents v table of contents preface introduction and overview design philosophy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix purpose of this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix intended audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix users manual overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix amd documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xx e86 family xx chapter 1 features and performance 1.1 key features and benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 distinctive characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 application considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.3.1 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.3.2 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3.3 serial communications port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.4 third-party development support products . . . . . . . . . . . 1-6 chapter 2 programming 2.1 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1 processor status flags register . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 memory organization and address generation . . . . . . . . . 2-3 2.3 i/o space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.5 segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.6 data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 chapter 3 system overview 3.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 pins that are used by emulators . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.2 bus operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.3 bus interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.3.1 nonmultiplexed address bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.3.2 byte write enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.3.3 pseudo static ram (psram) support . . . . . . . . . . . . . . . . . . . . 3-19 3.4 clock and power management unit . . . . . . . . . . . . . . . . . . . . 3-20 3.4.1 phase-locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.4.2 crystal-driven clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.4.3 external source clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.4.4 system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.4.5 power-save operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 chapter 4 peripheral control block 4.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1 peripheral control block relocation register (relreg, offset feh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.1.2 reset configuration register (rescon, offset f6h). . . . . . . . . . 4-5 4.1.3 processor release level register (prl, offset f4h) . . . . . . . . . . 4-6 4.1.4 power-save control register (pdcon, offset f0h). . . . . . . . . . . 4-7 4.2 initialization and processor reset . . . . . . . . . . . . . . . . . . . . . 4-8
table of contents vi chapter 5 chip select unit 5.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 chip select timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 ready and wait-state programming . . . . . . . . . . . . . . . . . . . . . 5-2 5.4 chip select overlap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.5 chip select registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.5.1 upper memory chip select register (umcs, offset a0h) . . . . . . 5-4 5.5.2 low memory chip select register (lmcs, offset a2h) . . . . . . . . 5-6 5.5.3 midrange memory chip select register (mmcs, offset a6h) . . . 5-8 5.5.4 pcs and mcs auxiliary register (mpcs, offset a8h) . . . . . . . . 5-10 5.5.5 peripheral chip select register (pacs, offset a4h) . . . . . . . . . 5-12 chapter 6 refresh control unit 6.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.1 memory partition register (mdram, offset e0h) . . . . . . . . . . . . 6-1 6.1.2 clock prescaler register (cdram, offset e2h) . . . . . . . . . . . . . . 6-2 6.1.3 enable rcu register (edram, offset e4h) . . . . . . . . . . . . . . . . 6-2 chapter 7 interrupt control unit 7.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.1 definitions of interrupt terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.2 interrupt conditions and sequence . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.1.3 interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.1.4 software exceptions, traps, and nmi . . . . . . . . . . . . . . . . . . . . . . 7-6 7.1.5 interrupt acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.1.6 interrupt controller reset conditions . . . . . . . . . . . . . . . . . . . . . . 7-8 7.2 master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.2.1 fully nested mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.2.2 cascade mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.2.3 special fully nested mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.2.4 operation in a polled environment . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.2.5 end-of-interrupt write to the eoi register . . . . . . . . . . . . . . . . . 7-11 7.3 master mode interrupt controller registers . . . . . . . . 7-12 7.3.1 int0 and int1 control registers (i0con, offset 38h, i1con, offset 3ah) (master mode) . . . . . . 7-13 7.3.2 int2 and int3 control registers (i2con, offset 3ch, i3con, offset 3eh) (master mode) . . . . . . 7-15 7.3.3 int4 control register (i4con, offset 40h) (master mode) . . . . 7-16 7.3.4 timer and dma interrupt control registers (tcucon, offset 32h, dma0con, offset 34h, dma1con, offset 36h) (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 7.3.5 watchdog timer interrupt control register (wdcon, offset 42h) (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 7.3.6 serial port interrupt control register (spicon, offset 44h) (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 7.3.7 interrupt status register (intsts, offset 30h) (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 7.3.8 interrupt request register (reqst, offset 2eh) (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 7.3.9 in-service register (inserv, offset 2ch) (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 7.3.10 priority mask register (primsk, offset 2ah) (master mode). . . 7-23 7.3.11 interrupt mask register (imask, offset 28h) (master mode) . . . 7-24 7.3.12 poll status register (pollst, offset 26h) (master mode). . . . . 7-25 7.3.13 poll register (poll, offset 24h) (master mode). . . . . . . . . . . . . 7-26 7.3.14 end-of-interrupt register (eoi, offset 22h) (master mode) . . . . 7-27 7.4 slave mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
table of contents vii 7.4.1 slave mode interrupt nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 7.4.2 slave mode interrupt controller registers . . . . . . . . . . . . . . . . . 7-28 7.4.3 timer and dma interrupt control registers (t0intcon, offset 32h, t1intcon, offset 38h, t2intcon, offset 3ah, dma0con, offset 34h, dma1con, offset 36h) (slave mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29 7.4.4 interrupt status register (intsts, offset 30h) (slave mode) . . 7-30 7.4.5 interrupt request register (reqst, offset 2eh) (slave mode) . 7-31 7.4.6 in-service register (inserv, offset 2ch) (slave mode) . . . . . . 7-32 7.4.7 priority mask register (primsk, offset 2ah) (slave mode). . . . 7-33 7.4.8 interrupt mask register (imask, offset 28h) (slave mode) . . . . 7-34 7.4.9 specific end-of-interrupt register (eoi, offset 22h) (slave mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35 7.4.10 interrupt vector register (intvec, offset 20h) (slave mode) . . 7-36 chapter 8 timer control unit 8.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 programmable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2.1 timer operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2.2 timer 0 and timer 1 mode and control registers (t0con, offset 56h, t1con, offset 5eh) . . . . . . . . . . . . . . . . . . 8-3 8.2.3 timer 2 mode and control register (t2con, offset 66h) . . . . . . 8-5 8.2.4 timer count registers (t0cnt, offset 50h, t1cnt, offset 58h, t2cnt, offset 60h) . . . 8-6 8.2.5 timer maxcount compare registers (t0cmpa, offset 52h, t0cmpb, offset 54h, t1cmpa, offset 5ah, t1cmpb, offset 5ch, t2cmpa, offset 62h) . . . . . . . . . . . . . . . . 8-7 chapter 9 dma controller 9.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2 dma operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3 programmable dma registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.3.1 dma control registers (d0con, offset cah, d1con, offset dah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.3.2 dma transfer count registers (d0tc, offset c8h, d1tc, offset d8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.3.3 dma destination address high register (high order bits) (d0dsth, offset c6h, d1dsth, offset d6h) . . 9-6 9.3.4 dma destination address low register (low order bits) (d0dstl, offset c4h, d1dstl, offset d4h) . . . . . . . . . . . . . . . . 9-7 9.3.5 dma source address high register (high order bits) (d0srch, offset c2h, d1srch, offset d2h) . . . . . . . . . . . . . . . 9-8 9.3.6 dma source address low register (low order bits) (d0srcl, offset c0h, d1srcl, offset d0h) . . . . . . . . . . . . . . . . 9-9 9.4 dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.4.1 synchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.4.2 dma acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4.3 dma priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4.4 dma programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4.5 dma channels on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 chapter 10 asynchronous serial port 10.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2 programmable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2.1 serial port control register (spct, offset 80h) . . . . . . . . . . . . . 10-2 10.2.2 serial port status register (spsts, offset 82h) . . . . . . . . . . . . 10-4 10.2.3 serial port transmit data register (sptd, offset 84h) . . . . . . . 10-5 10.2.4 serial port receive data register (sprd, offset 86h). . . . . . . . 10-6 10.2.5 serial port baud rate divisor register (spbaud, offset 88h). . 10-7
table of contents viii chapter 11 synchronous serial interface 11.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1.1 four-pin interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2 programmable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2.1 synchronous serial status register (sss, offset 10h). . . . . . . . 11-3 11.2.2 synchronous serial control register (ssc, offset 12h) . . . . . . . 11-4 11.2.3 synchronous serial transmit 1 register (ssd1, offset 14h) synchronous serial transmit 0 register (ssd0, offset 16h) . . . 11-5 11.2.4 synchronous serial receive register (ssr, offset 18h) . . . . . . 11-6 11.3 ssi programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 chapter 12 programmable i/o pins 12.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2 pio mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.2.1 pio mode 1 register (piomode1, offset 76h) . . . . . . . . . . . . . 12-3 12.2.2 pio mode 0 register (piomode0, offset 70h) . . . . . . . . . . . . . 12-3 12.3 pio direction registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.3.1 pio direction 1 register (pdir1, offset 78h) . . . . . . . . . . . . . . 12-4 12.3.2 pio direction 0 register (pdir0, offset 72h) . . . . . . . . . . . . . . 12-4 12.4 pio data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12.4.1 pio data register 1 (pdata1, offset 7ah) . . . . . . . . . . . . . . . . 12-5 12.4.2 pio data register 0 (pdata0, offset 74h) . . . . . . . . . . . . . . . . 12-5 12.5 open-drain outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 appendix a register summary
table of contents ix list of figures figure 1-1 am186es microcontroller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 figure 1-2 am188es microcontroller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 figure 1-3 basic functional system design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 figure 2-1 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 figure 2-2 processor status flags register (f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 figure 2-3 physical address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 figure 2-4 memory and i/o space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 figure 2-5 supported data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 figure 3-1 am186es microcontroller address busnormal read and write operation . 3-21 figure 3-2 am186es microcontrollerread and write with address bus disable in effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 figure 3-3 am188es microcontroller address busnormal read and write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 figure 3-4 am188es microcontrollerread and write with address bus disable in effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 figure 3-5 oscillator configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 figure 3-6 clock organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 figure 4-1 peripheral control block relocation register . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 figure 4-2 reset configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 figure 4-3 processor release level register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 figure 4-4 auxiliary configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 figure 4-5 system configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 figure 5-1 upper memory chip select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 figure 5-2 low memory chip select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 figure 5-3 midrange memory chip select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 figure 5-4 pcs and mcs auxiliary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 figure 5-5 peripheral chip select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 figure 6-1 memory partition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 figure 6-2 clock prescaler register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 figure 6-3 enable rcu register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 figure 6-4 watchdog timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 figure 7-1 external interrupt acknowledge bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 figure 7-2 fully nested (direct) mode interrupt controller connections . . . . . . . . . . . . . 7-10 figure 7-3 cascade mode interrupt controller connections . . . . . . . . . . . . . . . . . . . . . . . 7-11 figure 7-4 int0 and int1 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 figure 7-5 int2 and int3 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 figure 7-6 int4 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 figure 7-7 timer/dma interrupt control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 figure 7-8 serial port 0/1 interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 figure 7-9 interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 figure 7-10 interrupt request register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 figure 7-11 interrupt in-service register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 figure 7-12 priority mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 figure 7-13 interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 figure 7-14 poll status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 figure 7-15 poll register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 figure 7-16 example eoi assembly code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 figure 7-17 end-of-interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 figure 7-18 timer and dma interrupt control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29 figure 7-19 interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30 figure 7-20 interrupt request register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31 figure 7-21 interrupt in-service register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32 figure 7-22 priority mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 figure 7-23 interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34 figure 7-24 specific end-of-interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35 figure 7-25 interrupt vector register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36 figure 8-1 typical waveform behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
table of contents x figure 8-1 timer 0 and timer 1 mode and control registers . . . . . . . . . . . . . . . . . . . . . . . 8-3 figure 8-2 timer 2 mode and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 figure 8-3 timer count registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 figure 8-4 timer maxcount compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 figure 9-1 dma unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 figure 9-2 dma control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 figure 9-3 dma transfer count registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 figure 9-4 dma destination address high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 figure 9-5 dma destination address low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 figure 9-6 dma source address high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 figure 9-7 dma source address low register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 figure 9-8 source-synchronized dma transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 figure 9-9 destination synchronized dma transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 figure 10-10 dce/dte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 figure 10-11 cts/rtr protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 figure 10-1 serial port control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 figure 10-2 serial port 0/1 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 figure 10-3 serial port 0/1 transmit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 figure 10-4 serial port receive 0/1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 figure 10-5 serial port 0/1 baud rate divisor registers . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 figure 11-1 programmable i/o pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 figure 11-3 pio mode 0 register (piomode0, offset 70h) . . . . . . . . . . . . . . . . . . . . . . . . 11-3 figure 11-2 pio mode 1 register (piomode1, offset 76h) . . . . . . . . . . . . . . . . . . . . . . . . 11-3 figure 11-4 pio direction 1 register (pdir1, offset 78h) . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 figure 11-5 pio direction 0 register (pdir0, offset 72h) . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 figure 11-6 pio data 1 register (pdata1, offset 7ah) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 figure 11-7 pio data 0 register (pdata0, offset 74h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 figure a-1 internal register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-4
table of contents xi list of tables table 2-1 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 table 2-2 segment register selection rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 table 2-3 memory addressing mode examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 table 3-1 numeric pio pin designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 table 3-2 alphabetic pio pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 table 3-3 programming am186es microcontroller bus width . . . . . . . . . . . . . . . . . . . . 3-24 table 4-1 peripheral control block register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 table 4-2 processor release level (prl) values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 table 4-3 initial register state after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 table 5-1 chip select register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 table 5-2 umcs block size programming values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 table 5-3 lmcs block size programming values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 table 5-4 mcs block size programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 table 5-5 pcs address ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 table 5-6 pcs 3Cpcs 0 wait-state encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 table 6-7 watchdog timer count settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 table 6-8 watchdog timer duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 table 7-1 am186es and am188es microcontroller interrupt types . . . . . . . . . . . . . . . . . 7-4 table 7-2 interrupt controller registers in master mode . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 table 7-3 priority level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 table 7-4 priority level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 table 7-5 interrupt controller registers in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 table 7-6 priority level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 table 8-1 timer control unit register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 table 9-1 dma controller register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 table 9-2 synchronization type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 table 9-3 maximum dma transfer rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 table 10-4 serial port external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 table 10-1 asynchronous serial port register summary . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 table 10-2 dma control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 table 10-3 serial port mode settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 table 10-4 common baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 table 11-1 pio pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 table 11-2 pio mode and pio direction settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 table a-1 internal register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-1
table of contents xii
introduction and overview xiii preface introduction and overview design philosophy amds am186 and am188 family of microcontrollers is based on the architecture of the original 8086 and 8088 microcontrollers, and currently includes the 80c186, 80c188, 80l186, 80l188, am186 ? em, am188 ? em, am186emlv, am188emlv, am186es, am188es, am186eslv, am188eslv, am186er, and am188er microcontrollers. the am186em and am188em microcontrollers provide a natural migration path for 80c186/ 188 designs that need performance and cost enhancements. the am186em and am188em microcontrollers provide a low-cost, high-performance solution for embedded system designers who want to use the x86 architecture. by integrating multiple functional blocks with the cpu, the am186em and am188em microcontrollers eliminate the need for off-chip system-interface logic. it is possible to implement a fully functional system with rom and ram, serial interfaces, and custom i/o capability without additional system-interface logic. the am186em and am188em microcontrollers can operate at frequencies up to 40 mhz. the microcontrollers include an on-board pll so that the input clock can be one-to-one with the internal processor clock. the am186em and am188em microcontrollers are available in versions operating at 20, 25, 33, and 40 mhz. purpose of this manual this manual describes the technical features and programming interface of the am186em and am188em microcontrollers. the complete instruction set is documented in the am186 and am188 family instruction set manual, order #21267. intended audience this manual is intended for computer hardware and software engineers and system architects who are designing or are considering designing systems based on the am186em and am188em microcontrollers. users manual overview this manual contains information on the am186em and am188em microcontrollers and is essential for system architects and design engineers. additional information is available in the form of data sheets, application notes, and other documentation that is provided with software products and hardware-development tools. the information in this manual is organized into 12 chapters and 1 appendix. n chapter 1 introduces the features and performance aspects of the am186em and am188em microcontrollers. n chapter 2 describes the programmer?s model of the am186 and am188 family microcontrollers, including an instruction set overview and register model. n chapter 3 provides an overview of the system interfaces , along with clocking features.
introduction and overview xiv n chapter 4 provides a description of the peripheral control block along with power management and reset configuration. n chapter 5 provides a description of the chip select unit . n chapter 6 provides a description of the refresh control unit . n chapter 7 provides a description of the on-chip interrupt controller . n chapter 8 describes the timer control unit . n chapter 9 describes the dma controller . n chapter 10 describes the asynchronous serial port . n chapter 11 describes the synchronous serial interface . n chapter 12 describes the programmable i/o pins . n appendix a includes a complete summary of peripheral registers and fields . for complete information on the am186em and am188em microcontroller pin lists, timing, thermal characteristics, and physical dimensions, please refer to the am186em/emlv and am188em/emlv microcontrollers data sheet (order# 19168). amd documentation e86 family order no. document title 19168 am186em/emlv and am188em/emlv microcontrollers data sheet hardware documentation: pin descriptions, functional descriptions, absolute maximum ratings, operating ranges, switching characteristics and waveforms, connection diagrams and pinouts, and package physical dimensions. 21267 am186 and am188 family instruction set manual provides a detailed description and examples for each instruction included in the am186 and am188 family instruction set. 19255 fusione86 sm catalog provides information on tools that speed an e86 family embedded product to market. includes products from expert suppliers of embedded development so- lutions. 20071 e86 family support tools brief lists available e86 family software and hardware development tools, as well as contact information for suppliers. 21058 fusione86 development tools reference cd provides a single-source multimedia tool for customer evaluation of amd prod- ucts, as well as fusion partner tools and technologies that support the e86 family of microcontrollers and microprocessors. technical documentation for the e86 family is included on the cd in pdf format. to order literature, contact the nearest amd sales office or call 800-222-9323 (in the u.s. and canada) or direct dial from any location 512-602-5651. literature is also available in postscript and pdf formats on the amd web site. to access the amd home page, go to http://www.amd.com. to download documents and software, ftp to ftp.amd.com and log on as anonymous using your e-mail address as a password. or via your web browser, go to ftp://ftp.amd.com.
features and performance 1-1 chapter 1 features and performance compared to the 80c186/188 microcontrollers, the am186 ? em and am188 ? em microcontrollers enable designers to increase performance and functionality, while reducing the cost, size, and power consumption of embedded systems. the am186em and am188em microcontrollers are cost-effective, enhanced versions of the amd 80c186/ 188 devices. the am186em and am188em microcontrollers are the ideal upgrade for 80c186/188 designs requiring 80c186/188-compatibility, increased performance, serial communications, and a glueless bus interface. developed exclusively for the embedded marketplace, the am186em and am188em microcontrollers increase the performance of existing 80c186/188 systems while decreasing their cost. because the am186em and am188em microcontrollers integrate on-chip peripherals and offer up to twice the performance of an 80c186/188, they are ideal upgrade solutions for customers requiring more integration and performance than their present x86 solution delivers. 1.1 key features and benefits the am186em and am188em microcontrollers extend the amd family of microcontrollers based on the industry-standard x86 architecture. the am186em and am188em microcontrollers deliver higher performance and more integration than the 80c186/188 core microcontrollers. upgrading to the am186em or am188em microcontrollers is attractive for the following reasons: n minimized total system cost the new peripherals and on-chip system-interface logic reduce the cost of existing 80c186 designs. n x86 software compatibility 80c186/188-compatible and upward-compatible with the amd e86 family. n enhanced performance the am186em and am188em microcontrollers can provide increased performance over 80c186/188 systems, and the nonmultiplexed address bus offers faster, unbuffered access to memory. n no wait-state operation at 40 mhz with 70-ns memories. n enhanced functionality the new and enhanced on-chip peripherals of the am186em and am188em microcontrollers include an asynchronous serial port, a watchdog timer interrupt, an additional interrupt pin, a high-speed synchronous serial interface, a psram controller, a 16-bit reset configuration register, enhanced chip-select functionality, 32 programmable i/os, and additional interrupt signals. the am186em and am188em microcontrollers are part of the amd e86 family of embedded microcontrollers and microprocessors based on the x86 architecture. the 16-bit members of the e86 family, referred to throughout this manual as the am186 and am188 family, include the 80c186, 80c188, 80l186, 80l188, am186emlv, am188emlv, am186es, am188es, am186eslv, am188eslv, am186er, and am188er microcontrollers.
features and performance 1-2 the am186em and am188em microcontrollers are designed to meet the most common requirements of embedded products developed for the office automation, mass storage, communications, and general embedded markets. applications include disk drives, hand- held terminals, fax machines, terminals, printers, photocopiers, feature phones, cellular phones, pbxs, multiplexers, modems, and industrial controls. 1.2 distinctive characteristics a block diagram of each microcontroller is shown in figure 1-1 and figure 1-2. the am186em microcontroller uses a 16-bit external bus, while the am188em microcontroller has an 8-bit external bus. the am186em and am188em microcontrollers provide the following features: n high performance: 20-, 25-, 33-, and 40-mhz operating frequencies support for zero wait-state operation at 40 mhz with 70-ns memory 1-mbyte memory address space and 64-kbyte i/o space n new features remove the requirement for a 2x clock input and provide faster access to memory: phase-locked loop (pll) allows processor to operate at the clock input frequency nonmultiplexed address bus n new integrated peripherals increase functionality while reducing system cost: 32 programmable i/o (pio) pins asynchronous serial port allows full-duplex, 7-bit or 8-bit data transfers pseudo-static ram (psram) controller includes auto refresh capability reset configuration register synchronous serial interface allows high-speed, half-duplex, bidirectional data transfer to and from application-specific integrated circuits (asics) additional external interrupts n familiar 80c186 peripherals: two independent dma channels programmable interrupt controller with five external interrupts three programmable 16-bit timers timer 1 can be configured to provide a watchdog timer interrupt programmable memory and peripheral chip-select logic programmable wait-state generator power-save mode n software-compatible with the 80c186/188 microcontroller n widely available native development tools, applications, and system software n available in the following packages: 100-pin, thin quad flat pack (tqfp) 100-pin, plastic quad flat pack (pqfp)
features and performance 1-3 figure 1-1 am186em microcontroller block diagram note: * all pio signals are shared with other physical pins. see the pin descriptions in chapter 3 and table 3-1 on page 3-9 for information on shared functions. s 2Cs 0 interrupt control unit timer control unit dma unit bus interface unit execution unit chip-select unit clock and power management unit control registers 16-bit count registers max count a registers 16-bit count registers 20-bit destination pointers 20-bit source pointers control registers control registers control registers 01 (wdt)2 0 1 max count b registers refresh control unit control registers control registers control registers clkoutb clkouta int4 int3/inta 1/irq int2/inta 0 int1/select int0 tmrout0 tmrout1 drq0 drq1 v cc gnd tmrin0 tmrin1 ardy srdy dt/r den hold hlda asynchronous serial port synchronous serial interface txd rxd sclk sdata sden0 sden1 nmi a19Ca0 ad15Cad0 ale bhe /aden wr wlb whb rd res lcs /once 0 mcs 2Cmcs 0 pcs 6/a2 pcs 3Cpcs 0 pcs 5/a1 ucs /once 1 x2 x1 control registers psram control unit mcs 3/rfsh pio unit pio31C pio0* control registers s6/ uzi clkdiv 2
features and performance 1-4 figure 1-2 am188em microcontroller block diagram note: * all pio signals are shared with other physical pins. see the pin descriptions in chapter 3 and table 3-1 on page 3-9 for information on shared functions. s 2Cs 0 interrupt control unit timer control unit dma unit bus interface unit execution unit chip-select unit clock and power management unit control registers 16-bit count registers max count a registers 16-bit count registers 20-bit destination pointers 20-bit source pointers control registers control registers control registers 01 (wdt)2 0 1 max count b registers refresh control unit control registers control registers control registers clkoutb clkouta int4 int3/inta 1/irq int2/inta 0 int1/select int0 tmrout0 tmrout1 drq0 drq1 v cc gnd tmrin0 tmrin1 ardy srdy dt/r den hold hlda asynchronous serial port synchronous serial interface txd rxd sclk sdata sden0 sden1 nmi s6/ a19Ca0 ad7Cad0 ale wr wb rd res lcs /once 0 mcs 2Cmcs 0 pcs 6/a 2 pcs 3Cpcs 0 pcs 5/a 1 ucs /once 1 x2 x1 uzi control registers psram control unit mcs 3/rfsh pio unit pio31C pio0* control registers ao15Cao8 rfsh 2/aden clkdiv 2
features and performance 1-5 1.3 application considerations the integration enhancements of the am186em and am188em microcontrollers provide a high-performance, low-system-cost solution for 16-bit embedded microcontroller designs. the nonmultiplexed address bus (a19 Ca0) eliminates system-interface logic for memory devices, while the multiplexed address/data bus maintains the value of existing customer- specific peripherals and circuits within the upgraded design. the nonmultiplexed address bus is available in addition to the 80c186 and 80c188 microcontrollers multiplexed address/data bus (ad15Cad0). the two buses can operate simultaneously or the ad15Cad0 bus can be configured to operate only during the data phase of a bus cycle. see the bhe /aden and rfsh 2/aden pin descriptions in chapter 3, and see section 5.5.1 and section 5.5.2 for additional information regarding the ad15Cad0 address enabling and disabling. figure 1-3 illustrates a functional system design that uses the integrated peripheral set to achieve high performance with reduced system cost. figure 1-3 basic functional system design 1.3.1 clock generation the integrated pll clock-generation circuitry of the am186em and am188em microcontrollers allows the use of a times-one crystal frequency. the design in figure 1-3 achieves 40-mhz cpu operation with a 40-mhz crystal. the integrated pll lowers system cost by reducing the cost of the crystal and reduces electromechanical interference (emi) in the system. x2 x1 rs-232 level converter txd rxd lcs ucs whb wlb we address data oe cs we rd we address data oe cs we ad15Cad0 a19Ca0 flash prom static ram serial port am186em microcontroller 40-mhz crystal
features and performance 1-6 1.3.2 memory interface the integrated memory controller logic of the am186em and am188em microcontrollers provides a direct address bus interface to memory devices. the use of an external address latch controlled by the address latch enable (ale) signal is not required. individual byte write-enable signals are provided to eliminate the need for external high/ low-byte, write-enable circuitry. the maximum bank size programmable for the memory chip-select signals is increased to 512 kbytes to facilitate the use of high-density memory devices. improved memory timing specifications enables the use of no-wait-state memories with 70-ns access times at 40-mhz cpu operation. this reduces overall system cost significantly by allowing the use of commonly available memory devices. figure 1-3 illustrates an am186em microcontroller-based sram configuration. the memory interface requires the following: n the processor a19 Ca0 bus connects to the memory address inputs. n the ad bus connects directly to the data inputs/outputs. n the chip selects connect to the memory chip-select inputs. read operations require that the rd output connects to the sram output enable (oe ) input pins. write operations require that the byte write enables connect to the sram write enable (we ) input pins. the design uses 2-mbit (256-kbyte) memory technology to fully populate the available address space. two flash prom devices provide 512 kbytes of nonvolatile program storage, and two static ram devices provide 512 kbytes of variable storage area. 1.3.3 serial communications port the integrated universal asynchronous receiver/transmitter (uart) controller in the am186em and am188em microcontrollers eliminates the need for external logic to implement a communications interface. the integrated uart generates the serial clock from the cpu clock so that no external time-base oscillator is required. figure 1-3 shows a minimal implementation of an rs-232 console or modem communications port. the rs-232 to cmos voltage-level converter is required for the proper electrical interface with the external device. the am186em and am188em microcontrollers also include a synchronous serial interface. for more information, see chapter 11. 1.4 third-party development support products the fusione86 program of partnerships for application solutions provides the customer with an array of products designed to meet critical time-to-market needs. products and solutions available from the amd fusione86 partners include emulators, hardware and software debuggers, board-level products, and software development tools, among others. in addition, mature development tools and applications for the x86 platform are widely available in the general marketplace.
programming 2-1 chapter 2 programming all members of the am186 and am188 family of microcontrollers, including the am186em and am188em, contain the same basic set of registers, instructions, and addressing modes, and are compatible with the original industry-standard 186/188 parts. 2.1 register set the base architecture of the am186em and am188em microcontrollers has 14 registers, as shown in figure 2-1. these registers are grouped into the following categories: n general registers eight 16-bit general purpose registers can be used for arithmetic and logical operands. four of these (ax, bx, cx, and dx) can be used as 16-bit registers or split into pairs of separate 8-bit registers (ah, al, bh, bl, ch, cl, dh, and dl). the destination index (di) and source index (si) general-purpose registers are used for data movement and string instructions. the base pointer (bp) and stack pointer (sp) general-purpose registers are used for the stack segment and point to the bottom and top of the stack, respectively. base and index registers four of the general-purpose registers (bp, bx, di, and si) can also be used to determine offset addresses of operands in memory. these registers can contain base addresses or indexes to particular locations within a segment. the addressing mode selects the specific registers for operand and address calculations. stack pointer register all stack operations (pop, popa, popf, push, pusha, pushf) utilize the stack pointer. the stack pointer register is always offset from the stack segment (ss) register, and no segment override is allowed. n segment registers four 16-bit special-purpose registers (cs, ds, es, and ss) select, at any given time, the segments of memory that are immediately addressable for code (cs), data (ds and es), and stack (ss) memory. (for usage, refer to section 2.2.) n status and control registers two 16-bit special-purpose registers record or alter certain aspects of the processor statethe instruction pointer (ip) register contains the offset address of the next sequential instruction to be executed and the processor status flags (flags) register contains status and control flag bits (see figure 2-1 and figure 2-2). note that the am186em and am188em microcontrollers have additional on-chip peripheral registers, which are external to the processor. these external registers are not accessible by the instruction set. however, because the processor treats these peripheral registers like memory, instructions that have operands that access memory can also access peripheral registers. the above processor registers, as well as the additional on-chip peripheral registers, are described in the chapters that follow.
programming 2-2 figure 2-1 register set 2.1.1 processor status flags register the 16-bit processor status flags register (figure 2-2) records specific characteristics of the result of logical and arithmetic instructions (bits 0, 2, 4, 6, 7, and 11) and controls the operation of the microcontroller within a given operating mode (bits 8, 9, and 10). after an instruction is executed, the value of the flags may be set (to 1), cleared/reset (set to 0), unchanged, or undefined. the term undefined means that the flag value prior to the execution of the instruction is not preserved, and the value of the flag after the instruction is executed cannot be predicted. figure 2-2 processor status flags register (f) bits 15 C12 reserved bit 11: overflow flag (of) set if the signed result cannot be expressed within the number of bits in the destination operand, cleared otherwise. bit 10: direction flag (df) causes string instructions to auto-decrement the appropriate index registers when set. clearing df causes auto-increment. ah byte addressable (8-bit register names shown) loop/shift/repeat/count base registers code segment data segment stack segment extra segment processor status flags instruction pointer general registers status and control registers segment registers 15 0 15 0 7 0 7 0 15 0 cs flags ip 16-bit register name special register functions ds ss es ax dx cx bx bp si di sp dh ch bh al dl cl bl index registers stack pointer multiply/divide i/o instructions base pointer source index destination index 16-bit register name 15 70 if tf sf zf res cf pf reserved res af res of df
programming 2-3 bit 9: interrupt-enable flag (if) when set, enables maskable interrupts to cause the cpu to transfer control to a location specified by an interrupt vector. bit 8: trace flag (tf) when set, a trace interrupt occurs after instructions execute. tf is cleared by the trace interrupt after the processor status flags are pushed onto the stack. the trace service routine can continue tracing by popping the flags back with an interrupt return (iret) instruction. bit 7: sign flag (sf) set equal to high-order bit of result (0 if 0 or positive, 1 if negative). bit 6: zero flag (zf) set if result is 0; cleared otherwise. bit 5: reserved bit 4: auxiliary carry (af) set on carry from or borrow to the low-order 4 bits of the al general-purpose register; cleared otherwise. bit 3: reserved bit 2: parity flag (pf) set if low-order 8 bits of result contain an even number of 1 bits; cleared otherwise. bit 1: reserved bit 0: carry flag (cf) set on high-order bit carry or borrow; cleared otherwise. 2.2 memory organization and address generation memory is organized in sets of segments. each segment is a linear contiguous sequence of 64k (2 16 ) 8-bit bytes. memory is addressed using a two-component address that consists of a 16-bit segment value and a 16-bit offset. the offset is the number of bytes from the beginning of the segment (the segment address), to the data or instruction that is being accessed. the processor forms the physical address of the target location by taking the segment address, shifting it to the left 4 bits (multiplying by 16), and adding this to the 16-bit offset. the result is the 20-bit address of the target data or instruction. this allows for a 1-mbyte physical address size. for example, if the segment register is loaded with 12a4h and the offset is 0022h, the resultant address is 12a62h (see figure 2-3). to find the result: 1. the segment register contains 12a4h. 2. the segment register is shifted 4 places and is now 12a40h. 3. the offset is 0022h. 4. the shifted segment address (12a40h) is added to the offset (00022h) to get 12a62h. 5. this address is placed on the pins of the controller. all instructions that address operands in memory must specify (implicitly or explicitly) a 16- bit segment value and a 16-bit offset value. the 16-bit segment values are contained in one of four internal segment registers (cs, ds, es, and ss). see addressing modes on page 2-10 for more information on calculating the offset value. see segments on page 2-8 for more information on cs, ds, es, and ss. in addition to memory space, all am186 and am188 family processors provide 64k of i/o space (see figure 2-4).
programming 2-4 figure 2-3 physical address generation 2.3 i/o space the i/o space consists of 64k 8-bit or 32k 16-bit ports. the in and out instructions address the i/o space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the dx register. eight-bit port addresses are zero-extended so that a15Ca8 are low. i/o port addresses 00f8h through 00ffh are reserved. the am186em and am188em microcontrollers provide specific instructions for addressing i/o space. figure 2-4 memory and i/o space 2.4 instruction set each member of the am186 and am188 family of microcontrollers, including the am186em and am188em, share the standard 186 instruction set. an instruction can reference from zero to several operands. an operand can reside in a register, in the instruction itself, or in memory. specific operand addressing modes are discussed on page 2-10. table 2-1 lists the instructions for the am186em and am188em microcontrollers in alphabetical order. the am186 and am188 family instruction set manual, pid #21076, provides detailed information on the format and function of the following instructions. 1 2 a 4 0 0 0 0 2 2 1 2 a 6 2 1 2 a 4 0 0 2 2 segment base logical address shift left 4 bits physical address to memor y 15 0 19 0 19 0 15 0 15 0 offset memory space i/o space 1m 64k
programming 2-5 table 2-1 instruction set mnemonic instruction name aaa ascii adjust for addition aad ascii adjust for division aam ascii adjust for multiplication aas ascii adjust for subtraction adc add byte or word with carry add add byte or word and logical and byte or word bound detects values outside prescribed range call call procedure cbw convert byte to word clc clear carry flag cld clear direction flag cli clear interrupt-enable flag cmc complement carry flag cmp compare byte or word cmps compare byte or word string cwd convert word to doubleword daa decimal adjust for addition das decimal adjust for subtraction dec decrement byte or word by 1 div divide byte or word unsigned enter format stack for procedure entry esc escape to extension processor hlt halt until interrupt or reset idiv integer divide byte or word imul integer multiply byte or word in input byte or word inc increment byte or word by 1 ins input bytes or word string int interrupt into interrupt if overflow iret interrupt return ja/jnbe jump if above/not below or equal jae/jnb jump if above or equal/not below
programming 2-6 jb/jnae jump if below/not above or equal jbe/jna jump if below or equal/not above jc jump if carry jcxz jump if register cx = 0 je/jz jump if equal/zero jg/jnle jump if greater/not less or equal jge/jnl jump if greater or equal/not less jl/jnge jump if less/not greater or equal jle/jng jump if less or equal/not greater jmp jump jnc jump if not carry jne/jnz jump if not equal/not zero jno jump if not overflow jnp/jpo jump if not parity/parity odd jns jump if not sign jo jump if overflow jp/jpe jump if parity/parity even js jump if sign lahf load ah register from flags lds load pointer using ds lea load effective address leave restore stack for procedure exit les load pointer using es lock lock bus during next instruction lods load byte or word string loop loop loope/ loopz loop if equal/zero loopne/ loopnz loop if not equal/not zero mov move byte or word movs move byte or word string mul multiply byte or word unsigned neg negate byte or word nop no operation not logical not byte or word mnemonic instruction name
programming 2-7 or logical inclusive or byte or word out output byte or word pop pop word off stack popa pop all general register off stack popf pop flags off stack push push word onto stack pusha push all general registers onto stack pushf push flags onto stack rcl rotate left through carry byte or word rcr rotate right through carry byte or word rep repeat repe/repz repeat while equal/zero repne/ repnz repeat while not equal/not zero ret0 return from procedure rol rotate left byte or word ror rotate right byte or word sahf store ah register in flags sf, zf, af, pf, and cf sal shift left arithmetic byte or word sar shift right arithmetic byte or word sbb subtract byte or word with borrow scas scan byte or word string shl shift left logical byte or word shr shift right logical byte or word stc set carry flag std set direction flag sti set interrupt-enable flag stos store byte or word string sub subtract byte or word test test (logical and, flags only set) byte or word xchg exchange byte or word xlat translate byte xor logical exclusive or byte or word mnemonic instruction name
programming 2-8 2.5 segments the am186em and am188em use four segment registers: 1. data segment (ds): the processor assumes that all accesses to the programs variables are from the 64k space pointed to by the ds register. the data segment holds data, operands, etc. 2. code segment (cs): this 64k space is the default location for all instructions. all code must be executed from the code segment. 3. stack segment (ss): the processor uses the ss register to perform operations that involve the stack, such as pushes and pops. the stack segment is used for temporary space. 4. extra segment (es): usually this segment is used for large string operations and for large data structures. certain string instructions assume the extra segment as the segment portion of the address. the extra segment is also used (by using segment override) as a spare data segment. when a segment is not defined for a data movement instruction, its assumed to be a data segment. an instruction prefix can be used to override the segment register. for speed and compact instruction encoding, the segment register used for physical address generation is implied by the addressing mode used (see table 2-1). table 2-1 segment register selection rules 2.6 data types the am186em and am188em microcontrollers directly support the following data types: n integer a signed binary numeric value contained in an 8-bit byte or a 16-bit word. all operations assume a twos complement representation. n ordinal an unsigned binary numeric value contained in an 8-bit byte or a 16-bit word. n double word a signed binary numeric value contained in two sequential 16-bit addresses, or in a dx::ax register pair. n quad word a signed binary numeric value contained in four sequential 16-bit addresses. n bcd an unpacked byte representation of the decimal digits 0C9. n ascii a byte representation of alphanumeric and control characters using the ascii standard of character representation. n packed bcd a packed byte representation of two decimal digits (0C9). one digit is stored in each nibble (4 bits) of the byte. memory reference needed segment register used implicit segment selection rule local data data (ds) all data references instructions code (cs) instructions (including immediate data) stack stack (ss) all stack pushes and pops any memory references that use the bp register external data (global) extra (es) all string instruction references that use the di register as an index
programming 2-9 n string a contiguous sequence of bytes or words. a string can contain from 1 byte up to 64 kbyte. n pointer a 16-bit or 32-bit quantity, composed of a 16-bit offset component or a 16-bit segment base component plus a 16-bit offset component. in general, individual data elements must fit within defined segment limits. figure 2-5 graphically represents the data types supported by the am186em and am188em microcontrollers. figure 2-5 supported data types 7 0 signed byte magnitude magnitude 7 0 msb unsigned byte signed word magnitude msb +1 0 magnitude msb +3 +2 +1 0 signed quad word magnitude msb 63 48 47 32 31 16 15 0 unsigned word magnitude msb +1 0 7 0 7 0 7 0 +n +1 0 . . . 7 0 7 0 7 0 +n +1 0 . . . 7 0 7 0 7 0 +n +1 0 . . . binary coded decimal (bcd) bcd digit n bcd digit 1 bcd digit 0 ascii character n ascii character 1 ascii character 0 ascii most significant digit least significant digit packed bcd 7 0 7 0 +n +1 0 . . . byte/wordn byte/word1 byte/word0 string +3 +2 +1 0 segment base offset pointer 31 1615 0 0 15 +3 +2 +1 +6 +5 +4 +0 +7 15 14 8 7 0 70 signed double word sign bit sign bit sign bit sign bit
programming 2-10 2.7 addressing modes the am186em and am188em microcontrollers use eight categories of addressing modes to specify operands. two addressing modes are provided for instructions that operate on register or immediate operands; six modes are provided to specify the location of an operand in a memory segment. register and immediate operands n register operand mode the operand is located in one of the 8- or 16-bit registers. n immediate operand mode the operand is included in the instruction. memory operands a memory-operand address consists of two 16-bit components: a segment value and an offset. the segment value is supplied by a 16-bit segment register either implicitly chosen by the addressing mode or explicitly chosen by a segment override prefix. the offset, also called the effective address, is calculated by summing any combination of the following three address elements: 1. displacement an 8-bit or 16-bit immediate value contained in the instruction 2. base contents of either the bx or bp base registers 3. index contents of either the si or di index registers any carry from the 16-bit addition is ignored. eight-bit displacements are sign-extended to 16-bit values. combinations of the above three address elements define the following six memory addressing modes (see table 2-2): 1. direct mode the operand offset is contained in the instruction as an 8- or 16-bit displacement element. 2. register indirect mode the operand offset is in one of the registers bp, bx, di, or si. 3. based mode the operand offset is the sum of an 8- or 16-bit displacement and the contents of a base register (bx or bp). 4. indexed mode the operand offset is the sum of an 8- or 16-bit displacement and the contents of an index register (di or si). 5. based indexed mode the operand offset is the sum of the contents of a base register (bp or bx) and an index register (di or si). 6. based indexed mode with displacement the operand offset is the sum of a base registers contents, an index registers contents, and an 8-bit or 16-bit displacement. table 2-2 memory addressing mode examples addressing mode example direct mov ax, ds:4 register indirect mov ax, [si] based mov ax, [bx]4 indexed mov ax, [si]4 based indexed mov ax, [si][bx] based indexed with displacement mov ax, [si][bx]4
system overview 3-1 chapter 3 system overview this chapter contains descriptions of the am186em and am188em microcontroller pins, the bus interface unit, the clock and power management unit, and power-save operation. 3.1 pin descriptions pin terminology the following terms are used to describe the pins: input an input-only pin. output an output-only pin. input/output a pin that can be either input or output. synchronous synchronous inputs must meet setup and hold times in relation to clkouta. synchronous outputs are synchronous to clkouta. asynchronous inputs or outputs that are asynchronous to clkouta. a19Ca0 address bus (output, three-state, synchronous) the a19Ca0 pins supply nonmultiplexed memory or i/o addresses to the system one-half of a clkouta period earlier than the multiplexed address and data bus (ad15Cad0 on the am186em or ao15Cao8 and ad7Cad0 on the am188em). during a bus hold or reset condition, the address bus is in a high-impedance state. ad7Cad0 address and data bus (input/output, three-state, synchronous, level-sensitive) these time-multiplexed pins supply partial memory or i/o addresses, as well as data, to the system. this bus supplies the low-order 8 bits of an address to the system during the first period of a bus cycle (t 1 ), and it supplies data to the system during the remaining periods of that cycle (t 2 , t 3 , and t 4 ). the address phase of these pins can be disabled. see the aden description with the bhe /aden pin. when wlb is not asserted, these pins are three-stated during t 2 , t 3 , and t 4 . during a bus hold or reset condition, the address and data bus is in a high-impedance state. during a power-on reset, the address and data bus pins (ad15Cad0 for the am186em, ao15Cao8 and ad7Cad0 for the am188em) can also be used to load system configuration information into the internal reset configuration register.
system overview 3-2 ad15Cad8 address and data bus, am186em microcontroller only (input/output, three-state, synchronous, level-sensitive) ad15Cad8 these time-multiplexed pins supply partial memory or i/o addresses, as well as data, to the system. this bus supplies an address to the system during the first period of a bus cycle (t 1 ), and it supplies data to the system during the remaining periods of that cycle (t 2 , t 3 , and t 4 ). the address phase of these pins can be disabled. see the aden description with the bhe /aden pin. when whb is not asserted, these pins are three-stated during t 2 , t 3 , and t 4 . during a bus hold or reset condition, the address and data bus is in a high-impedance state. during a power-on reset, the address and data bus pins (ad15Cad0 for the am186em, ao15Cao8 and ad7Cad0 for the am188em) can also be used to load system configuration information into the internal reset configuration register. ao15Cao8 address-only bus, am188em microcontroller only (output, three-state, synchronous, level-sensitive) ao15Cao8 the address-only bus (ao15Cao8) contains valid high- order address bits from bus cycles t 1 Ct 4 . these outputs are floated during a bus hold or reset. on the am188em microcontroller, ao15Cao8 combine with ad7Cad0 to form a complete multiplexed address bus while ad7Cad0 is the 8-bit data bus. the address phase of these pins can be disabled during t 1 . see the aden description with the bhe /aden pin. during a power-on reset on the am188em microcontroller, the ao15C ao8 and ad7Cad0 pins can also be used to load system configuration information into an internal register for later use. ale address latch enable (output, synchronous) ale this pin indicates to the system that an address appears on the address and data bus (ad15Cad0 for the am186em or ao15Cao8 and ad7Cad0 for the am188em). the address is guaranteed valid on the trailing edge of ale. ardy asynchronous ready (input, asynchronous, level-sensitive) this pin indicates to the microcontroller that the addressed memory space or i/o device will complete a data transfer. the ardy pin accepts a rising edge that is asynchronous to clkouta and is active high. the falling edge of ardy must be synchronized to clkouta. to always assert the ready condition to the microcontroller, tie ardy high. if the system does not use ardy, tie the pin low to yield control to srdy.
system overview 3-3 bhe /aden bus high enable, am186em microcontroller only (three-state, output, synchronous) address enable, am186em microcontroller only (input, internal pullup) bhe during a memory access, this pin and the least significant address bit (ad0 and a0) indicate to the system which bytes of the data bus (upper, lower, or both) participate in a bus cycle. the bhe /aden and ad0 pins are encoded as shown in the following table. bhe is asserted during t 1 and remains asserted through t 3 and t w . bhe does not need to be latched. bhe floats during bus hold and reset. on the am186em microcontroller, wlb and whb implement the functionality of bhe and ad0 for high and low byte write enables. bhe /aden also signals dram refresh cycles when using the multiplexed address and data (ad) bus. a refresh cycle is indicated when both bhe /aden and ad0 are high. during refresh cycles, the a bus and the ad bus are not guaranteed to provide the same address during the address phase of the ad bus cycle. for this reason, the a0 signal cannot be used in place of the ad0 signal to determine refresh cycles. psram refreshes also provide an additional rfsh signal (see the mcs 3/rfsh pin description). aden if bhe /aden is held high or left floating during power-on reset, the address portion of the ad bus (ad15Cad0) is enabled or disabled during lcs and ucs bus cycles based on the da bit in the upper memory chip select (umcs) and low memory chip select (lmcs) registers. if the da bit is set, the memory address is accessed on the a19Ca0 pins. this mode of operation reduces power consumption. if bhe /aden is held low on power-on reset, the ad bus always drives both addresses and data. the pin is sampled one crystal clock cycle after the rising edge of res . see section 5.5.1 and section 5.5.2 for additional information on enabling and disabling the ad bus during the address phase of a bus cycle. clkouta clock output a (output, synchronous) this pin supplies the internal clock to the system. depending on the value of the power-save control (pdcon) register, clkouta operates at either the crystal input frequency (x1), the power-save frequency, or is three-stated. clkouta remains active during reset and bus hold conditions. bhe ad0 type of bus cycle 0 0 word transfer 0 1 high byte transfer (bits 15C8) 1 0 low byte transfer (bits 7C0) 1 1 refresh
system overview 3-4 clkoutb clock output b (output, synchronous) this pin supplies an additional clock to the system. depending on the value of the power-save control (pdcon) register, clkoutb operates at either the crystal input frequency (x1), the power-save frequency, or is three-stated. clkoutb remains active during reset and bus hold conditions. den data enable (output, three-state, synchronous) this pin supplies an output enable to an external data-bus transceiver. den is asserted during memory, i/o, and interrupt acknowledge cycles. den is deasserted when dt/r changes state. den floats during a bus hold or reset condition. drq1Cdrq0 dma requests (input, synchronous, level-sensitive) these pins indicate to the microcontroller that an external device is ready for dma channel 1 or 0 to perform a transfer. drq1Cdrq0 are level triggered and internally synchronized. the drq signals are not latched and must remain active until serviced. dt/r data transmit or receive (output, three-state, synchronous) this pin indicates which direction data should flow through an external data-bus transceiver. when dt/r is asserted high, the microcontroller transmits data. when this pin is deasserted low, the microcontroller receives data. dt/r floats during a bus hold or reset condition. gnd ground these pins connect the system ground to the microcontroller. hlda bus hold acknowledge (output, synchronous) this pin is asserted high to indicate to an external bus master that the microcontroller has relinquished control of the local bus. when an external bus master requests control of the local bus (by asserting hold), the microcontroller completes the bus cycle in progress and then relinquishes control of the bus to the external bus master by asserting hlda and floating den , rd , wr , s 2Cs 0, ad15Cad0, s6, a19Ca0, bhe , whb , wlb , and dt/r , and then driving the chip selects ucs , lcs , mcs 3Cmcs 0, pcs 6Cpcs 5, and pcs 3Cpcs 0 high. when the external bus master has finished using the local bus, it indicates this to the microcontroller by deasserting hold. the microcontroller responds by deasserting hlda. if the microcontroller requires access to the bus (i.e., for refresh), it will deassert hlda before the external bus master deasserts hold. the external bus master must be able to deassert hold and allow the microcontroller access to the bus. hold bus hold request (input, synchronous, level-sensitive) this pin indicates to the microcontroller that an external bus master needs control of the local bus. for more information, see the hlda pin description. the am186em and am188em microcontrollers hold latency time, that is, the time between hold request and hold acknowledge, is a function of the activity occurring in the processor when the hold
system overview 3-5 request is received. a hold request is second only to dram refresh requests in priority of activity requests received by the processor. this implies that if a hold request is received just as a dma transfer begins, the hold latency can be as great as 4 bus cycles. this occurs if a dma word transfer operation is taking place (am186em microcontroller only) from an odd address to an odd address. this is a total of 16 clock cycles or more if wait states are required. in addition, if locked transfers are performed, the hold latency time is increased by the length of the locked transfer. int0 maskable interrupt request 0 (input, asynchronous) this pin indicates to the microcontroller that an interrupt request has occurred. if the int0 pin is not masked, the microcontroller transfers program execution to the location specified by the int0 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. to guarantee the interrupt is recognized, the device issuing the request must continue asserting int0 until the request is acknowledged. int1/select maskable interrupt request 1 (input, asynchronous) slave select (input, asynchronous) int1 this pin indicates to the microcontroller that an interrupt request has occurred. if the int1 pin is not masked, the microcontroller transfers program execution to the location specified by the int1 vector in the microcontroller interrupt vector table. interrupt requests are synchro- nized internally, and can be edge-triggered or level-triggered. to guar- antee the interrupt is recognized, the device issuing the request must continue asserting int1 until the request is acknowledged. select when the microcontroller interrupt control unit is operating as a slave to an external master interrupt controller, this pin indicates to the microcontroller that an interrupt type appears on the address and data bus. the int0 pin must indicate to the microcontroller that an interrupt has occurred before the select pin indicates to the microcontroller that the interrupt type appears on the bus. int2/inta 0 maskable interrupt request 2 (input, asynchronous) interrupt acknowledge 0 (output, synchronous) int2 this pin indicates to the microcontroller that an interrupt request has occurred. if the int2 pin is not masked, the microcontroller transfers program execution to the location specified by the int2 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. to guarantee the interrupt is recognized, the device issuing the request must continue asserting int2 until the request is acknowledged. int2 becomes inta 0 when int0 is configured in cascade mode. inta 0 when the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on int0. the peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type.
system overview 3-6 int3/inta 1/irq maskable interrupt request 3 (input, asynchronous) interrupt acknowledge 1 (output, synchronous) slave interrupt request (output, synchronous) int3 this pin indicates to the microcontroller that an interrupt request has occurred. if the int3 pin is not masked, the microcontroller then transfers program execution to the location specified by the int3 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally, and they can be edge-triggered or level- triggered. to guarantee the interrupt is recognized, the device issuing the request must continue asserting int3 until the request is acknowledged. int3 becomes inta 1 when int1 is configured in cascade mode. inta 1 when the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on int1. the peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. irq when the microcontroller interrupt control unit is operating as a slave to an external master interrupt controller, this pin lets the microcontroller issue an interrupt request to the external master interrupt controller. int4 maskable interrupt request 4 (input, asynchronous) this pin indicates to the microcontroller that an interrupt request has occurred. if the int4 pin is not masked, the microcontroller then transfers program execution to the location specified by the int4 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally, and they can be edge-triggered or level- triggered. to guarantee the interrupt is recognized, the device issuing the request must continue asserting int4 until the request is acknowledged. lcs /once 0 lower memory chip select (output, synchronous, internal pullup) once mode request 0 (input) lcs this pin indicates to the system that a memory access is in progress to the lower memory block. the base address and size of the lower memory block are programmable up to 512 kbytes. lcs is held high during a bus hold condition. once 0 during reset this pin and ucs /once 1 indicate to the microcontroller the mode in which it should operate. once 0 and once 1 are sampled on the rising edge of res . if both pins are asserted low, the microcontroller enters once mode; otherwise, it operates normally. in once mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. to guarantee that the microcontroller does not inadvertently enter once mode, once 0 has a weak internal pullup resistor that is active only during a reset.
system overview 3-7 mcs 3/rfsh midrange memory chip select 3 (output, synchronous, internal pullup) automatic refresh (output, synchronous) mcs 3 this pin indicates to the system that a memory access is in progress to the fourth region of the midrange memory block. the base address and size of the midrange memory block are programmable. mcs 3 is held high during a bus hold condition. in addition, this pin has a weak internal pullup resistor that is active during reset. rfsh this pin provides a signal timed for auto refresh to psram devices. it is only enabled to function as a refresh pulse when the psram mode bit is set in the lmcs register. an active low pulse is generated for 1.5 clock cycles with an adequate deassertion period to ensure overall auto refresh cycle time is met. mcs 2Cmcs 0 midrange memory chip selects (output, synchronous, internal pullup) these pins indicate to the system that a memory access is in progress to the corresponding region of the midrange memory block. the base address and size of the midrange memory block are programmable. mcs 2Cmcs 0 are held high during a bus hold condition. in addition, they have weak internal pullup resistors that are active during a reset. nmi nonmaskable interrupt (input, synchronous, edge-sensitive) this pin indicates to the microcontroller that an interrupt request has occurred. the nmi signal is the highest priority hardware interrupt and, unlike the int4Cint0 pins, cannot be masked. the microcontroller always transfers program execution to the location specified by the nonmaskable interrupt vector in the microcontroller interrupt vector table when nmi is asserted. although nmi is the highest priority interrupt source, it does not participate in the priority resolution process of the maskable interrupts. there is no bit associated with nmi in the interrupt in-service or interrupt request registers. this means that a new nmi request can interrupt an executing nmi interrupt service routine. as with all hardware interrupts, the if (interrupt flag) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. however, if maskable interrupts are re-enabled by software in the nmi interrupt service routine, via the sti instruction for example, the fact that an nmi is currently in service will not have any effect on the priority resolution of maskable interrupt requests. for this reason, it is strongly advised that the interrupt service routine for nmi does not enable the maskable interrupts. an nmi transition from low to high is latched and synchronized internally, and it initiates the interrupt at the next instruction boundary. to guarantee that the interrupt is recognized, the nmi pin must be asserted for at least one clkouta period. pcs 3Cpcs 0 peripheral chip selects (output, synchronous) these pins indicate to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. pcs 3Cpcs 0 are held high during a bus hold
system overview 3-8 or reset condition. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note: pcs 4 is not available on the am186em and am188em micro- controllers. note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. pcs 5/a1 peripheral chip select 5 (output, synchronous) latched address bit 1 (output, synchronous) pcs 5 this pin indicates to the system that a memory access is in progress to the sixth region of the peripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. pcs 5 is held high during a bus hold or reset condition. it is also held high during reset. note: unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. a1 when the ex bit in the mcs and pcs auxiliary register is 0, this pin supplies an internally latched address bit 1 to the system. during a bus hold condition, a1 retains its previously latched value. pcs 6/a2 peripheral chip select 6 (output, synchronous) latched address bit 2 (output, synchronous) pcs 6 this pin indicates to the system that a memory access is in progress to the seventh region of the peripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. pcs 6 is held high during a bus hold or reset condition. note: unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the original 80c186 and 80c188 microcontrollers. a2 when the ex bit in the mcs and pcs auxiliary register is 0, this pin supplies an internally latched address bit 2 to the system. during a bus hold condition, a2 retains its previously latched value. pio31Cpio0 (shared) programmable i/o pins (input/output, asynchronous, open-drain) the am186em and am188em microcontrollers provide 32 individually programmable i/o pins. the pins that are multiplexed with pio31Cpio0 are listed in table 3-1 and table 3-2. each pio can be programmed with the following attributes: pio function (enabled/disabled), direction (input/output), and weak pullup or pulldown. see chapter 12 for the pio control registers. after power-on reset, the pio pins default to various configurations. the column titled power-on reset state in table 3-1 and table 3-2 lists the defaults for the pios. the system initialization code must reconfigure any pios as required.
system overview 3-9 the a19Ca17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address ffff0h. the dt/r , den , and srdy pins also default to normal operation on power-on reset. table 3-1 pio pin assignmentsnumeric listing notes: 1. these pins are used by emulators. (emulators also use s 2Cs 0 , res , nmi, clkouta, bhe , ale, ad15Cad0, and a16Ca0. 2. these pins revert to normal operation if bhe /aden (am186em) or rfsh 2/aden (am188em) is held low during power-on reset. 3. when used as a pio, input with pullup option available. 4. when used as a pio, input with pulldown option available. pio no. associated pin power-on reset status 0 tmrin1 input with pullup 1 tmrout1 input with pulldown 2pcs 6/a2 input with pullup 3pcs 5/a1 input with pullup 4dt/r normal operation (3) 5den normal operation (3) 6 srdy normal operation (4) 7 (1) a17 normal operation (3) 8 (1) a18 normal operation (3) 9 (1) a19 normal operation (3) 10 tmrout0 input with pulldown 11 tmrin0 input with pullup 12 drq0 input with pullup 13 drq1 input with pullup 14 mcs 0 input with pullup 15 mcs 1 input with pullup 16 pcs 0 input with pullup 17 pcs 1 input with pullup 18 pcs 2 input with pullup 19 pcs 3 input with pullup 20 sclk input with pullup 21 sdata input with pullup 22 sden0 input with pulldown 23 sden1 input with pulldown 24 mcs 2 input with pullup 25 mcs 3/rfsh input with pullup 26 (1,2) uzi input with pullup 27 txd input with pullup 28 rxd input with pullup 29 (1,2) s6/clkdiv 2 input with pullup 30 int4 input with pullup 31 int2 input with pullup
system overview 3-10 table 3-2 pio pin assignmentsalphabetic listing notes: 1. these pins are used by emulators. (emulators also use s 2Cs 0 , res , nmi, clkouta, bhe , ale, ad15Cad0, and a16Ca0. 2. these pins revert to normal operation if bhe /aden (am186em) or rfsh 2/aden (am188em) is held low during power-on reset. 3. when used as a pio, input with pullup option available. 4. when used as a pio, input with pulldown option available. associated pin pio no. power-on reset status a17 (1) 7 normal operation (3) a18 (1) 8 normal operation (3) a19 (1) 9 normal operation (3) den 5 normal operation (3) drq0 12 input with pullup drq1 13 input with pullup dt/r 4 normal operation (3) int2 31 input with pullup int4 30 input with pullup mcs 0 14 input with pullup mcs 1 15 input with pullup mcs 2 24 input with pullup mcs 3/rfsh 25 input with pullup pcs 0 16 input with pullup pcs 1 17 input with pullup pcs 2 18 input with pullup pcs 3 19 input with pullup pcs 5/a1 3 input with pullup pcs 6/a2 2 input with pullup rxd 28 input with pullup s6/clkdiv 2 (1,2) 29 input with pullup sclk 20 input with pullup sdata 21 input with pullup sden0 22 input with pulldown sden1 23 input with pulldown srdy 6 normal operation (4) tmrin0 11 input with pullup tmrin1 0 input with pullup tmrout0 10 input with pulldown tmrout1 1 input with pulldown txd 27 input with pullup uzi (1,2) 26 input with pullup
system overview 3-11 rd read strobe (output, synchronous, three-state) rd this pin indicates to the system that the microcontroller is performing a memory or i/o read cycle. rd is guaranteed not to be asserted before the address and data bus is floated during the address- to-data transition. rd floats during a bus hold condition. res reset (input, asynchronous, level-sensitive) this pin causes the microcontroller to perform a reset. when res is asserted, the microcontroller immediately terminates its present activity, clears its internal logic, and cpu control is transferred to the reset address ffff0h. res must be held low for at least 1 ms. the assertion of res can be asynchronous to clkouta because res is synchronized internally. for proper initialization, v cc must be within specifications, and clkouta must be stable for more than four clkouta periods during which res is asserted. the microcontroller begins fetching instructions approximately 6.5 clkouta periods after res is deasserted. this input is provided with a schmitt trigger to facilitate power-on res generation via an rc network. rfsh 2/aden refresh 2 (three-state, output, synchronous) address enable (input, internal pullup) rfsh 2 available on the am188em microcontroller only, rfsh 2/ aden is asserted low to signify a dram refresh bus cycle. the use of rfsh 2/aden to signal a refresh is not valid when psram mode is selected. instead, the mcs 3/rfsh signal is provided to the psram. aden if rfsh 2/aden is held high or left floating on power-on reset, the ad bus (ao15Cao8 and ad7Cad0) is enabled or disabled during the address portion of lcs and ucs bus cycles based on the da bit in the lmcs and umcs registers. if the da bit is set, the memory address is accessed on the a19Ca0 pins. this mode of operation reduces power consumption. there is a weak internal pullup resistor on rfsh 2/aden , so no external pullup is required. if rfsh 2/aden is held low on power-on reset, the ad bus drives both addresses and data. the pin is sampled one crystal clock cycle after the rising edge of res . rfsh 2/aden is three-stated during bus holds and once mode. see section 5.5.1 and section 5.5.2 for additional information on enabling and disabling the ad bus during the address phase of a bus cycle. rxd receive data (input, asynchronous) this pin supplies asynchronous serial receive data to the microcontroller uart. s 2Cs 0 bus cycle status (output, three-state, synchronous) these pins indicate to the system the type of bus cycle in progress. s 2 can be used as a logical memory or i/o indicator, and s 1 can be used as a data transmit or receive indicator. s 2Cs 0 float during bus hold and hold acknowledge conditions. the s 2Cs 0 pins are encoded as shown in the following table.
system overview 3-12 s6/clkdiv 2 bus cycle status bit 6 (output, synchronous) clock divide by 2 (input, internal pullup) s6 during the second and remaining periods of a cycle (t 2 , t 3 , and t 4 ), this pin is asserted high to indicate a dma-initiated bus cycle. during a bus hold or reset condition, s6 floats. clkdiv 2 if s6/clkdiv 2 is held low during power-on reset, the chip enters clock divide-by-2 mode where the processor clock is derived by dividing the external clock input by 2. if this mode is selected, the pll is disabled. the pin is sampled on the rising edge of res . if s6 is to be used as pio29 in input mode, the device driving pio29 must not drive the pin low during power-on reset. s6/pio29 defaults to a pio input with pullup, so the pin does not need to be driven high externally. sclk serial clock (output, synchronous, three-state) this pin supplies the synchronous serial interface (ssi) clock to a slave device, allowing transmit and receive operations to be synchronized between the microcontroller and the slave. sclk is derived from the microcontroller internal clock and then divided by 2, 4, 8, or 16, depending on register settings. an access to any of the ssr or ssd registers activates sclk for eight sclk cycles (see figure 11-5 and figure 11-6 on page 11-8). when sclk is inactive, it is held high by the microcontroller. sdata serial data (input/output, synchronous) this pin transmits and receives synchronous serial interface (ssi) data to and from a slave device. when sdata is inactive, a weak keeper holds the last value of sdata on the pin. sden1Csden0 serial data enables (output, synchronous) these pins enable data transfers on ports 1 and 0 of the synchronous serial interface (ssi). the microcontroller asserts either sden1 or sden0 at the beginning of a transfer and deasserts it after the transfer is complete. when sden1Csden0 are inactive, they are held low by the microcontroller. s 2 s 1 s 0 bus cycle 0 0 0 interrupt acknowledge 0 0 1 read data from i/o 0 1 0 write data to i/o 0 1 1 halt 1 0 0 instruction fetch 1 0 1 read data from memory 1 1 0 write data to memory 1 1 1 none (passive)
system overview 3-13 srdy synchronous ready (input, synchronous, level-sensitive) this pin indicates to the microcontroller that the addressed memory space or i/o device will complete a data transfer. the srdy pin accepts an active-high input synchronized to clkouta. using srdy instead of ardy allows a relaxed system timing because of the elimination of the one-half clock period required to internally synchronize ardy. to always assert the ready condition to the microcontroller, tie srdy high. if the system does not use srdy, tie the pin low to yield control to ardy. tmrin0 timer input 0 (input, synchronous, edge-sensitive) this pin supplies a clock or control signal to the internal microcontroller timer 0. after internally synchronizing a low-to-high transition on tmrin0, the microcontroller increments the timer. tmrin0 must be tied high if not being used. tmrin1 timer input 1 (input, synchronous, edge-sensitive) this pin supplies a clock or control signal to the internal microcontroller timer 1. after internally synchronizing a low-to-high transition on tmrin1, the microcontroller increments the timer. tmrin1 must be tied high if not being used. tmrout0 timer output 0 (output, synchronous) this pin supplies to the system either a single pulse or a continuous waveform with a programmable duty cycle. tmrout0 is floated during a bus hold or reset. tmrout1 timer output 1 (output, synchronous) this pin supplies to the system either a single pulse or a continuous waveform with a programmable duty cycle. it can also be programmed as a watchdog timer. tmrout1 is floated during a bus hold or reset. txd transmit data (output, asynchronous) this pin supplies asynchronous serial transmit data from the microcontroller uart to the system. ucs /once 1 upper memory chip select (output, synchronous) once mode request 1 (input, internal pullup) ucs this pin indicates to the system that a memory access is in progress to the upper memory block. the base address and size of the upper memory block are programmable up to 512 kbytes. ucs is held high during a bus hold condition. after power-on reset, ucs is asserted because the processor begins executing at ffff0h and the default configuration for the ucs chip select is 64 kbytes from f0000h to fffffh. see section 5.5.1. once 1 during reset this pin and once 0 indicate to the microcontroller the mode in which it should operate. once 0 and once 1 are sampled on the rising edge of res . if both pins are asserted low, the microcontroller enters once mode; otherwise, it operates normally. in once mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. to guarantee that the microcontroller does not inadvertently enter once mode, once 1 has a weak internal pullup resistor that is active only during a reset.
system overview 3-14 uzi upper zero indicate (output, synchronous) this pin lets the designer determine whether an access to the interrupt vector table is in progress by oring it with bits 15C10 of the address and data bus (ad15Cad10 on the am186em and ao15Cao10 on the am188em). uzi is the logical or of the inverted a19Ca16 bits, and it asserts in the first period of a bus cycle and is held throughout the cycle. this pin should be allowed to float or should be pulled high at reset. if this pin is low at the negation of reset, the am186em and am188em microcontrollers will enter a reserved clock test mode. v cc power supply (input) these pins supply power (+5 v) to the microcontroller. whb write high byte, am186em microcontroller only (output, three-state, synchronous) this pin and wlb indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. in 80c186 designs, this information is provided by bhe , the least-significant address bit (ad0), and by wr . however, by using whb and wlb , the standard system-interface logic and external address latch that were required are eliminated. whb is asserted with ad15Cad8. whb is the logical or of bhe and wr . this pin floats during reset. wlb /wb write low byte, am186em microcontroller only (output, three-state, synchronous) write byte, am188em microcontroller only (output, three-state, synchronous) wlb this pin and whb indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. in 80c186 designs, this information is provided by bhe , the least-significant address bit (ad0), and by wr . however, by using whb and wlb , the standard system interface logic and external address latch that were required are eliminated. wlb is asserted with ad7Cad0. wlb is the logical or of ad0 and wr . this pin floats during reset. wb on the am188em microcontroller, this pin indicates a write to the bus. wb uses the same early timing as the nonmultiplexed address bus. wb is associated with ad7Cad0. this pin floats during reset. wb is the logical or of whb and wlb , which are not present on the am188em microcontroller. wr write strobe (output, synchronous) wr this pin indicates to the system that the data on the bus is to be written to a memory or i/o device. wr floats during a bus hold or reset condition.
system overview 3-15 x1 crystal input (input) this pin and the x2 pin provide connections for a fundamental mode or third-overtone parallel-resonant crystal used by the internal oscillator circuit. to provide the microcontroller with an external clock source, connect the source to the x1 pin and leave the x2 pin unconnected. x2 crystal output (output) this pin and the x1 pin provide connections for a fundamental mode or third-overtone parallel-resonant crystal used by the internal oscillator circuit. to provide the microcontroller with an external clock source, leave the x2 pin unconnected and connect the source to the x1 pin. 3.1.1 pins that are used by emulators the following pins are used by emulators: a19Ca0, ao15Cao8, ad7Cad0, ale, bhe / aden (on the am186em), clkouta, rfsh 2/aden (on the am188em), rd , s 2Cs 0, s6/ clkdiv 2, and uzi . emulators require that s6/clkdiv 2 and uzi be configured in their normal functionality, that is, as s6 and uzi . if bhe /aden (on the am186em) or rfsh 2/aden (on the am188em) is held low during the rising edge of res , s6 and uzi are configured in their normal functionality, instead of as pios, at reset.
system overview 3-16 3.2 bus operation the industry-standard 80c186 and 80c188 microcontrollers use a multiplexed address and data (ad) bus. the address is present on the ad bus only during the t 1 clock phase. the am186em and am188em microcontrollers continue to provide the multiplexed ad bus and, in addition, provide a nonmultiplexed address (a) bus. the a bus provides an address to the system for the complete bus cycle (t 1 Ct 4 ). for systems where power consumption is a concern, it is possible to disable the address from being driven on the ad bus on the am186em microcontroller and on the ad and ao buses on the am188em microcontroller during the normal address portion of the bus cycle for accesses to ucs and/or lcs address spaces. in this mode, the affected bus is placed in a high impedance state during the address portion of the bus cycle. this feature is enabled through the da bits in the umcs and lmcs registers. when address disable is in effect, the number of signals that assert on the bus during all normal bus cycles to the associated address space is reduced, thus decreasing power consumption, reducing processor switching noise, and preventing bus contention with memory devices and peripherals when operating at high clock rates. on the am188em microcontroller, the address is driven on a015Ca08 during the data portion of the bus cycle, regardless of the setting of the da bits. if the aden pin is pulled low during processor reset, the value of the da bits in the umcs and lmcs registers is ignored and the address is driven on the ad bus for all accesses, thus preserving the industry-standard 80c186 and 80c188 microcontrollers multiplexed address bus and providing support for existing emulation tools. figure 3-1 on page 3-17 shows the affected signals during a normal read or write operation for an am186em microcontroller. the address and data will be multiplexed onto the ad bus. figure 3-2 on page 3-17 shows an am186em microcontroller bus cycle when address bus disable is in effect. this results in the ad bus operating in a nonmultiplexed data-only mode. the a bus will provide the address during a read or write operation. figure 3-3 on page 3-18 shows the affected signals during a normal read or write operation for an am188em microcontroller. the multiplexed address/data mode is compatible with 80c188 microcontrollers and might be used to take advantage of existing logic or peripherals. figure 3-4 on page 3-18 shows an am188em microcontroller bus cycle when address bus disable is in effect. the address and data are not multiplexed. the ad7Cad0 signals will have only data on the bus, while the a bus will have the address during a read or write operation. the ao bus will also have the address during t 2 Ct 4 .
system overview 3-17 figure 3-1 am186em microcontroller address busnormal read and write operation figure 3-2 am186em microcontrollerread and write with address bus disable in effect clkouta t 1 t 2 t 3 t 4 ad15Cad0 (read) data ad15Cad0 (write) lcs or ucs address data address address phase data phase a19Ca0 address mcs x, pcs x clkouta t 1 t 2 t 3 t 4 ad15Cad0 (write) data lcs , ucs ad15Cad8 (read) ad7Cad0 (read) address phase data data phase data a19Ca0 address
system overview 3-18 figure 3-3 am188em microcontroller address busnormal read and write operation figure 3-4 am188em microcontrollerread and write with address bus disable in effect clkouta t 1 t 2 t 3 t 4 ad7Cad0 (read) data ao15Cao8 (read or write) ad7Cad0 (write) address address data address address phase data phase a19Ca0 address lcs or ucs mcs x, pcs x clkouta t 1 t 2 t 3 t 4 ad7Cad0 (read) data address ao15Cao8 lcs , ucs ad7Cad0 (write) data address phase data phase a19Ca0 address
system overview 3-19 3.3 bus interface unit the bus interface unit controls all accesses to external peripherals and memory devices. external accesses include those to memory devices, as well as those to memory-mapped and i/o-mapped peripherals and the peripheral control block. the am186em and am188em microcontrollers provide an enhanced bus interface unit with the following features: n a nonmultiplexed address bus n separate byte write enables for high and low bytes in the am186em microcontroller n pseudo-static ram (psram) support the standard 80c186 multiplexed address and data bus requires system-interface logic and an external address latch. on the am186em and am188em microcontrollers, new byte write enables, psram control logic, and a new nonmultiplexed address bus can reduce design costs by eliminating external logic. timing diagrams for the operations described in this chapter appear in the am186em/emlv and am188em/emlv microcontrollers data sheet , order# 19168. 3.3.1 nonmultiplexed address bus the nonmultiplexed address bus (a19Ca0) is valid one-half clkouta cycle in advance of the address on the ad bus. when used in conjunction with the modified ucs and lcs outputs and the byte write enable signals, the a19Ca0 bus provides a seamless interface to sram, psram, and flash/eprom memory systems. 3.3.2 byte write enables the am186em microcontroller provides two signals that act as byte write enableswhb (write high byte, ad15Cad8) and wlb (write low byte, ad7Cad0). whb is the logical or of bhe and wr (whb is low when both bhe and wr are low). wlb is the logical or of ad0 and wr (wlb is low when both ad0 and wr are both low). the am188em microcontroller provides one signal for byte write enableswb (write byte). wb is the logical or of whb and wlb , which are not present on the am188em microcontroller. the byte write enables are driven in conjunction with the demultiplexed address bus as required for the write timing requirements of common srams. 3.3.3 pseudo static ram (psram) support the am186em and am188em microcontrollers support the use of psram devices in low memory chip select (lcs) space only. when psram mode is enabled, the timing for the lcs signal is modified by the chip select control unit to provide a cs precharge period during psram accesses. the 40-mhz timing of the am186em microcontroller is appropriate to allow 70-ns psram to run with one wait state. psram mode is enabled through a bit in the low memory chip select (lmcs) register. (see section 5.5.2 on page 5-6.) the psram feature is disabled on cpu reset. in addition to the lcs timing changes for psram precharge, the psram devices also require periodic refresh of all internal row addresses to retain their data. although refresh of psram can be accomplished several ways, the am186em and am188em microcontrollers implement auto refresh only. the microcontroller generates a refresh signal, rfsh , to the psram devices when psram mode is enabled. no refresh address is required by the psram when using the auto refresh mechanism. the rfsh signal is multiplexed with the mcs 3 signal pin. when psram mode is enabled, mcs 3 is not available for use as a chip select signal.
system overview 3-20 the refresh control unit must be programmed before accessing psram in lcs space. the refresh counter in the clock prescaler (cdram) register must be configured with the required refresh interval value. the ending address of lcs space and the ready and wait- state generation in the lmcs register must also be programmed. the refresh counter reload value in the cdram register should not be set to less than 18 (12h) in order to provide time for processor cycles within refresh. in psram mode, the refresh address counter must be set to 0000h to prevent another chip select from asserting. lcs is held high during a refresh cycle. the a19Ca0 bus is not used during refresh cycles. the lmcs register must be configured to external ready ignored (r2=1) with one wait state (r1Cr0=01b), and the psram mode enable bit (pse) must be set to 1. see section 5.5.2 on page 5-6. 3.4 clock and power management unit the clock and power management unit of the am186em and am188em microcontrollers includes a phase-locked loop (pll) and a second programmable system clock output (clkoutb). 3.4.1 phase-locked loop (pll) in a traditional 80c186/188 design, the crystal frequency is twice that of the desired internal clock. because of the internal pll on the am186em and am188em microcontrollers, the internal clock generated by the microcontroller (clkouta) is the same frequency as the crystal. the pll takes the crystal inputs (x1 and x2) and generates a 45/55% (worst case) duty cycle intermediate system clock of the same frequency. this feature removes the need for an external 2x oscillator, thereby reducing system cost. the pll is reset during power- on reset by an on-chip power-on reset (por) circuit. 3.4.2 crystal-driven clock source the internal oscillator circuit of the microcontroller is designed to function with a parallel resonant fundamental or third overtone crystal. because of the pll, the crystal frequency is equal to the processor frequency. replacement of a crystal with an lc or rc equivalent is not recommended. the x1 and x2 signals are connected to an internal inverting amplifier (oscillator) which provides, along with the external feedback loading, the necessary phase shift (figure 3-5). in such a positive feedback circuit, the inverting amplifier has an output signal (x2) 180 degrees out of phase of the input signal (x1). the external feedback network provides an additional 180-degree phase shift. in an ideal system, the input to x1 will have 360 or zero degrees of phase shift. the external feedback network is designed to be as close as possible to ideal. if the feedback network is not providing necessary phase shift, negative feedback will dampen the output of the amplifier and negatively affect the operation of the clock generator. values for the loading on x1 and x2 must be chosen to provide the necessary phase shift and crystal operation.
system overview 3-21 3.4.2.1 selecting a crystal when selecting a crystal, the load capacitance should always be specified (c l ). this value can cause variance in the oscillation frequency from the desired specified value (resonance). the load capacitance and the loading of the feedback network have the following relationship: where c s is the stray capacitance of the circuit. placing the crystal and c l in series across the inverting amplifier and tuning these values (c 1 , c 2 ) allows the crystal to oscillate at resonance. this relationship is true for both fundamental and third-overtone operation. finally, there is a relationship between c 1 and c 2 . to enhance the oscillation of the inverting amplifier, these values need to be offset with the larger load on the output (x2). equal values of these loads tend to balance the poles of the inverting amplifier. the characteristics of the inverting amplifier set limits on the following parameters for crystals: esr (equivalent series resistance).. .................. 80 ohm max drive level ............................................................... 1 mw max the recommended range of values for c 1 and c 2 are as follows: c 1 ............................................................................... 15 pf 20% c 2 ............................................................................... 22 pf 20% the specific values for c 1 and c 2 must be determined by the designer and are dependent on the characteristics of the chosen crystal and board design. figure 3-5 oscillator configurations (c 1 c 2 ) c l = (c 1 + c 2 ) + c s crystal am186em/ 200 pf note 1 x1 b. crystal configuration a. inverting amplifier configuration c 1 c 2 crystal c 1 c 2 microcontroller x2 am188em note 1 : use for third overtone mode xtal frequency l1 value (max 20 mhz 12 m h 20% 25 mhz 8.2 m h 20% 33 mhz 4.7 m h 20% 40 mhz 3.0 m h 20%
system overview 3-22 3.4.3 external source clock alternately, the internal oscillator can be driven from an external clock source. this source should be connected to the input of the inverting amplifier (x1) with the output (x2) not connected. 3.4.4 system clocks figure 3-6 shows the organization of the clocks. the 80c186 microcontroller system clock has been renamed clkouta. clkoutb is provided as an additional output. figure 3-6 clock organization clkouta and clkoutb operate at either the processor frequency or the pll frequency. the output drivers for both clocks are individually programmable for drive enable or disable. the second clock output (clkoutb) lets one clock run at the pll frequency and another clock run at the power-save frequency. individual drive enable bits allow selective enabling of just one or both of these clock outputs. 3.4.5 power-save operation the power-save mode reduces power consumption and heat dissipation, which can reduce power supply costs and size in all systems and extend battery life in portable systems. in power-save mode, operation of the cpu and internal peripherals continues at a slower clock frequency. when an interrupt occurs, the microcontroller automatically returns to its normal operating frequency on the internal clocks next rising edge of t 3 . note: power-save operation requires that clock-dependent devices be reprogrammed for clock frequency changes. software drivers must be aware of clock frequency. pll power-save divisor (/2 to /128) mux clkouta clkoutb drive enable x1, x2 processor internal clock time delay 6 2.5ns mux drive enable
peripheral control block 4-1 chapter 4 peripheral control block 4.1 overview the am186em and am188em microcontroller integrated peripherals are controlled by 16-bit read/write registers. the peripheral registers are contained within an internal 256- byte control blockthe peripheral control block. registers are physically located in the peripheral devices they control, but they are addressed as a single 256-byte block. figure 4-1 shows a map of the peripheral control block registers. code that is intended to execute on the am188em microcontroller should perform all writes to the pcb registers as byte writes. these writes will transfer 16 bits of data to the pcb register even if an 8-bit register is named in the instruction. for example, out dx, al results in the value of ax being written to the port address in dx . reads to the pcb should be done as word reads. code written in this manner will run correctly on the am188em microcontroller and on the am186em microcontroller. unaligned reads and writes to the pcb result in unpredictable behavior on both the am186em and am188em microcontrollers. the peripheral control block can be mapped into either memory or i/o space. the base address of the control block must be on an even 256-byte boundary (i.e., the lower eight bits of the base address are 00h). internal logic recognizes control block addresses and responds to bus cycles. during bus cycles to internal registers, the bus controller signals the operation externally (i.e., the rd , wr , status, address, and data lines are driven as in a normal bus cycle), but the data bus, srdy, and ardy are ignored. at reset, the peripheral control block relocation register is set to 20ffh, which maps the control block to start at ff00h in i/o space. an offset map of the 256-byte peripheral control register block is shown in figure 4-1. see section 4.1.1 on page 4-4 for a complete description of the peripheral control block relocation (relreg) register.
peripheral control block 4-2 figure 4-1 peripheral control block register map chapter 4 chapter 6 chapter 9 chapter 5 chapter 10 pcs and mcs auxiliary register a8 da memory partition register e0 pdcon register f0 reset configuration register f6 peripheral control block relocation register fe register name ww ww ww ww ww changed from 80c186 microcontroller. f4 note : gaps in offset addresses indicate reserved registers. offset (hexadecimal) e2 e4 d8 d6 d4 d2 ca c8 c6 c4 c2 c0 clock prescaler register enable rcu register dma 1 control register dma 1 transfer count register dma 1 destination address low register dma 1 source address high register dma 1 source address low register dma 0 control register dma 0 transfer count register dma 0 destination address high register dma 0 destination address low register d0 dma 0 source address low register dma 0 source address high register a6 a4 a2 a0 midrange memory chip select register peripheral chip select register low memory chip select register upper memory chip select register 80 serial port status register 82 84 serial port receive register 86 88 processor release level register dma 1 destination address high register serial port baud rate divisor register serial port transmit register serial port control register
peripheral control block 4-3 chapter 12 chapter 8 chapter 7 chapter 11 offset (hexadecimal) int2 control register int1 control register int0 control register dma 1 interrupt control register dma 0 interrupt control register timer interrupt control register interrupt status register interrupt request register in-service register priority mask register interrupt mask register poll status register poll register end-of-interrupt register interrupt vector register 10 12 synchronous serial transmit 1 register 14 16 18 3e 40 42 pio mode 0 register 70 72 74 register name ww ww ww changed from 80c186 microcontroller. 44 76 78 7a note : gaps in offset addresses indicate reserved registers. 5c 5e 60 62 66 50 52 54 56 58 5a timer 2 mode/control register timer 2 maxcount compare a register timer 2 count register timer 1 mode/control register timer 1 maxcount compare b register timer 1 maxcount compare a register timer 1 count register timer 0 mode/control register timer 0 maxcount compare b register timer 0 maxcount compare a register timer 0 count register int3 control register 3c 3a 38 36 34 32 30 2e 2c 2a 28 26 24 22 20 pio data 1 register pio direction 1 register pio mode 1 register pio data 0 register pio direction 0 register serial port interrupt control register watchdog timer control register int4 control register synchronous serial receive register synchronous serial transmit 0 register synchronous serial enable register synchronous serial status register
peripheral control block 4-4 4.1.1 peripheral control block relocation register (relreg, offset feh) the peripheral control block is mapped into either memory or i/o space by programming the peripheral control block relocation (relreg) register (see figure 4-2). this register is a 16-bit register at offset feh from the control block base address. the relreg register provides the upper 12 bits of the base address of the control block. the control block is effectively an internal chip select range. other chip selects can overlap the control block only if they are programmed to zero wait states and ignore external ready. if the control register block is mapped into i/o space, the upper four bits of the base address must be programmed as 0000b (since i/o addresses are only 16 bits wide). in addition to providing relocation information for the control block, the relreg register contains a bit that places the interrupt controller into either slave mode or master mode. at reset, the relreg register is set to 20ffh, which maps the control block to start at ff00h in i/o space. an offset map of the 256-byte peripheral control register block is shown in figure 4-1. figure 4-2 peripheral control block relocation register (relreg, offset feh) the value of the relreg register is 20ffh at reset. bit 15: reserved bit 14: slave/master (s/m ) configures the interrupt controller for slave mode when set to 1 and for master mode when set to 0. bit 13: reserved bit 12: memory/io space (m/io ) when set to 1, the peripheral control block (pcb) is located in memory space. when set to 0, the pcb is located in i/o space. bits 11C0: relocation address bits (r19Cr8) r19Cr8 define the upper address bits of the pcb base address. the lower eight bits (r7Cr0) default to 00h. r19Cr16 are ignored when the pcb is mapped to i/o space. 15 70 res s/m r19Cr8 res m/io
peripheral control block 4-5 4.1.2 reset configuration register (rescon, offset f6h) the reset configuration (rescon) register (see figure 4-3) in the peripheral control block latches system-configuration information that is presented to the processor on the address/ data bus (ad15Cad0 for the am186em or ao15Cao8 and ad7Cad1 for the am188em) during the rising edge of reset. the interpretation of this information is system-specific. the processor does not impose any predetermined interpretation, but simply provides a means for communicating this information to software. when the res input is asserted low, the contents of the address/data bus are written into the rescon register. the system can place configuration information on the address/data bus using weak external pullup or pulldown resistors, or using an external driver that is enabled during reset. the processor does not drive the address/data bus during reset. for example, the rescon register could be used to provide the software with the position of a configuration switch in the system. using weak external pullup and pulldown resistors on the address and data bus, the system could provide the microcontroller with a value corresponding to the position of a jumper during a reset. figure 4-3 reset configuration register (rescon, offset f6h) on reset, the rescon register is set to the value found on ad15Cad0. bits 15C0: reset configuration (rc) there is a one-to-one correspondence between address/data bus signals during the reset and the reset configuration registers bits. on the am186em microcontroller, ad15 corresponds to bit 15 of the reset configuration register, and so on. on the am188em microcontroller, ao15 corresponds to register bit 15, and ad7 corresponds to bit 7. once res is deasserted, the rescon register holds its value. this value can be read by software to determine the configuration information. the contents of the rescon register are read-only and remain valid until the next processor reset. 15 70 rc
peripheral control block 4-6 4.1.3 processor release level register (prl, offset f4h) the processor release level (prl) register (figure 4-4) is a read-only register that specifies the processor version. figure 4-4 processor release level register (prl, offset f4h) the values of the prl register are listed in table 4-1. bits 15C8: processor release level (prl) this field is an 8-bit, read-only identification number that specifies the processor release level. the values of the prl field for the am186em and am188em microcontrollers are shown in table 4-1. each release level is numbered one higher than the previous level. bits 7C0: reserved table 4-1 processor release level (prl) values prl value processor release level 01h c 02h d 03h e 04h f 15 70 reserved prl
peripheral control block 4-7 4.1.4 power-save control register (pdcon, offset f0h) figure 4-5 power-save control register (pdcon, offset f0h) the value of the pdcon register is 0000h at reset. bit 15: enable power-save mode (psen) when set to 1, enables power-save mode and divides the internal operating clock by the value in f2Cf0. psen is automatically cleared when an external interrupt, including those generated by on-chip peripheral devices, occurs. the value of the psen bit is not restored by the execution of an iret instruction. software interrupts (int instruction) and exceptions do not clear the psen bit, and interrupt service routines for these conditions should do so if desired. this bit is 0 after processor reset. bits 14C12: reserved read back as 0. bit 11: clkoutb output frequency (cbf) when set to 1, clkoutb follows the crystal input (pll) frequency. when set to 0, clkoutb follows the internal processor frequency (after the clock divisor). set to 0 on reset. clkoutb can be used as a full-speed clock source in power-save mode. bit 10: clkoutb drive disable (cbd) when set to 1, cbd three-states the clock output driver for clkoutb. when set to 0, clkoutb is driven as an output. set to 0 on reset. bit 9: clkouta output frequency (caf) when set to 1, clkouta follows the crystal input (pll) frequency. when set to 0, clkouta follows the internal processor frequency (after the clock divisor). set to 0 on reset. clkouta can be used as a full-speed clock source in power-save mode. bit 8: clkouta drive disable (cad) when set to 1, cad three-states the clock output driver for clkouta. when set to 0, clkouta is driven as an output. set to 0 on reset. bits 7C3: reserved read back as 0. bits 2C0: clock divisor select (f2Cf0) controls the division factor when power-save mode is enabled. allowable values are as follows: f2 f1 f0 divider factor 0 0 0 divide by 1 (2 0 ) 0 0 1 divide by 2 (2 1 ) 0 1 0 divide by 4 (2 2 ) 0 1 1 divide by 8 (2 3 ) 1 0 0 divide by 16 (2 4 ) 1 0 1 divide by 32 (2 5 ) 1 1 0 divide by 64 (2 6 ) 1 1 1 divide by 128 (2 7 ) 15 70 000 00000 cbd caf cad f1 f0 f2 psen cbf
peripheral control block 4-8 4.2 initialization and processor reset processor initialization or startup is accomplished by driving the res input pin low. res must be low during power-up to ensure proper device initialization. res forces the am186em and am188em microcontrollers to terminate all execution and local bus activity. no instruction or bus activity occurs as long as res is active. after res is deasserted and an internal processing interval elapses, the microcontroller begins execution with the instruction at physical location ffff0h. res also sets some registers to predefined values as shown in table 4-2.
peripheral control block 4-9 table 4-2 initial register state after reset note: registers not listed in this table are undefined at reset. register name mnemonic value at reset comments processor status flags f f002h interrupts disabled instruction pointer ip 0000h code segment cs ffffh boot address is ffff0h data segment ds 0000h ds = es = ss = 0000h extra segment es 0000h stack segment ss 0000h processor release level prl xxxxh prl xx = revision (lower half-word is undefined) peripheral control block relocation relreg 20ffh peripheral control block located at ff00h in i/o space and interrupt controller in master mode memory partition mdram 0000h refresh base address is 00000h enable rcu edram 0000h refresh disabled, counter = 0 upper memory chip select umcs f03bh ucs active for 64k from f0000h to fffffh, 3 wait states, external ready signal required low memory chip select lmcs undefined serial port control spct 0000h serial port interrupts disabled, no loopback, no break, brkval low, no parity, word length = 7, 1 stop bit, transmitter and receiver disabled pio direction 1 piodir1 ffffh pio mode 1 piomode1 0000h pio direction 0 piodir0 fc0fh pio mode 0 piomode0 0000h serial port interrupt control spicon 001fh serial port interrupt masked, priority 7 watchdog timer interrupt control wdcon 000fh watchdog timer interrupt masked, priority 7 int4 control i4con 000fh int4 interrupt masked, edge-triggered, priority 7 int3 control i3con 000fh int3 interrupt masked, edge-triggered, priority 7 int2 control i2con 000fh int2 interrupt masked, edge-triggered, priority 7 int1 control i1con 000fh int1 interrupt masked, edge-triggered, priority 7 int0 control i0con 000fh int0 interrupt masked, edge-triggered, priority 7 dma1 interrupt control dma1con 000fh dma1 interrupts masked, edge-triggered, priority 7 dma0 interrupt control dma0con 000fh dma0 interrupts masked, edge-triggered, priority 7 timer interrupt control tcucon 000fh timer interrupts masked, edge-triggered, priority 7 in-service inserv 0000h no interrupts are in-service priority mask primsk 0007h allow all interrupts based on priority interrupt mask imask 07fdh all interrupts masked (off) synchronous serial control ssc 0000h sclk = 1/2 clkouta, no data enabled synchronous serial status sss 0000h synchronous serial port not busy, no errors, no transmit or receive completed. dma 1 control d1con fff9h dma 0 control d0con fff9h
peripheral control block 4-10
chip select unit 5-1 chapter 5 chip select unit 5.1 overview the am186em and am188em microcontrollers contain logic that provides programmable chip select generation for both memories and peripherals. in addition, the logic can be programmed to provide ready or wait-state generation and latched address bits a1 and a2. the chip select lines are active for all memory and i/o cycles in their programmed areas, whether they are generated by the cpu or by the integrated dma unit. the am186em and am188em microcontrollers provide six chip select outputs for use with memory devices and six more for use with peripherals in either memory space or i/o space. the six memory chip selects can be used to address three memory ranges. each peripheral chip select addresses a 256-byte block offset from a programmable base address (see section 4.1.1 on page 4-4). the chip selects are programmed through the use of five 16-bit peripheral registers (table 5-1). the umcs register, offset a0h, is used to program the upper memory chip select (ucs ). the lmcs register, offset a2h, is used to program the lower memory chip select (lcs ). the midrange memory chip selects (mcs 3 Cmcs 0) are programmed through the use of two registersthe midrange memory chip select (mmcs) register, offset a6h and the pcs and mcs auxiliary (mpcs) register, offset a8h. in addition to its use in configuring the mcs chip selects, the mpcs register and the pacs register are used to program the peripheral chip selects (pcs 6Cpcs 5 and pcs 3Cpcs 0). note: the pcs 4 chip select is not implemented on the am186em and am188em microcontrollers. table 5-1 chip select register summary note: a read or write will enable a chip select register. offset register mnemonic register name affected pins comments a0h umcs upper memory chip select ucs ending address is fixed at fffffh a2h lmcs lower memory chip select lcs starting address is fixed at 00000h a4h pacs peripheral chip select pcs 6Cpcs 5 pcs 3Cpcs 0 block size is fixed at 256 bytes a6h mmcs midrange chip select mcs 3Cmcs 0 starting address and block size are programmable a8h mpcs pcs and mcs auxiliary pcs 6Cpcs 5 pcs 3Cpcs 0 mcs 3Cmcs 0 affects both pcs and mcs chip selects
chip select unit 5-2 except for the ucs chip select, which is active on reset as discussed in section 5.5.1, chip selects are not activated until the associated registers have been accessed. (an access is any read or write operation.) for this reason, the chip select registers should not be read by the processor initialization code until after they have been written with valid data. the lcs chip select is activated when the lmcs register is accessed, the mcs chip selects are activated after both the mmcs and mpcs registers have been accessed, and the pcs chip selects are activated after both the pacs and mpcs registers have been accessed. 5.2 chip select timing the timing for the ucs and lcs outputs has been modified from the 80c186 and 80c188 microcontrollers. these outputs now assert in conjunction with the demultiplexed address bus (a19Ca0) for normal memory timing. to make these outputs available earlier in the bus cycle, the number of programmable memory size selections has been reduced. the mcs 3Cmcs 0 and pcs chip selects assert with the ad bus. 5.3 ready and wait-state programming the am186em and am188em microcontrollers can be programmed to sense a ready signal for each of the peripheral or memory chip select lines. the ready signal can be either the ardy or srdy signal. each chip select control register (umcs, lmcs, mmcs, pacs, and mpcs) contains a single-bit field, r2, that determines whether the external ready signal is required or ignored. when r2 is set to 1, external ready is ignored. when r2 is set to 0, external ready is required. the number of wait states to be inserted for each access to a peripheral or memory region is programmable. zero wait states to 15 wait states can be inserted for the pcs 3Cpcs 0 peripheral chip selects. zero wait states to three wait states can be inserted for all other chip selects. each of the chip select control registers, other than the pacs register (umcs, lmcs, mmcs, and mpcs), contains a two-bit field, r1Cr0, whose value determines the number of wait states from none to three to be inserted. a value of 00b in this field specifies no inserted wait states. a value of 11b specifies three inserted wait states. the pcs 3Cpcs 0 peripheral chip selects can be programmed for up to 15 wait states. the pacs register uses bits r3 and r1Cr0 for the additional wait states. when external ready is required (r2 is set to 0), internally programmed wait states will always complete before external ready can terminate or extend a bus cycle. for example, if the internal wait states are set to insert two wait states (r1Cr0 = 10b), the processor samples the external ready pin during the first wait cycle. if external ready is asserted at that time, the access completes after six cycles (four cycles plus two wait states). if external ready is not asserted during the first wait state, the access is extended until ready is asserted, which is followed by one more wait state followed by t 4 . 5.4 chip select overlap although programming the various chip selects on the am186em microcontroller so that multiple chip select signals are asserted for the same physical address is not recommended, it may be unavoidable in some systems. in such systems, the chip selects whose assertions overlap must have the same configuration for ready (external ready required or not required) and the number of wait states to be inserted into the cycle by the processor. the peripheral control block (pcb) is accessed using internal signals. these internal signals function as chip selects configured with zero wait states and no external ready. therefore, the pcb can be programmed to addresses that overlap external chip select signals if those external chip selects are programmed to zero wait states with no external ready required.
chip select unit 5-3 when overlapping an additional chip select with either the lcs or ucs chip selects, it must be noted that setting the disable address (da) bit in the lmcs or umcs register will disable the address from being driven on the ad bus for all accesses for which the associated chip select is asserted, including any accesses for which multiple chip selects assert. the mcs and pcs chip select pins can be configured as either chip selects (normal function) or as pio inputs or outputs. it should be noted; however, that the ready and wait state generation logic for these chip selects is in effect, regardless of their configurations as chip selects or pios. this means that if these chip selects are enabled (by a read or write to the mmcs and mpcs registers for the mcs chip selects, or by a read or write to the pacs and mpcs registers for the pcs chip selects), the ready and wait state programming for these signals must agree with the programming for any other chip selects with which their assertion would overlap if they were configured as chip selects. although the pcs 4 signal is not available on an external pin, the ready and wait state logic for this signal still exists internal to the part. for this reason, the pcs 4 address space must follow the rules for overlapping chip selects. the ready and wait-state logic for pcs 6Cpcs 5 is disabled when these signals are configured as address bits a2Ca1. failure to configure overlapping chip selects with the same ready and wait state requirements may cause the processor to hang with the appearance of waiting for a ready signal. this behavior may occur even in a system in which ready is always asserted (ardy or srdy tied high). configuring pcs in i/o space with lcs or any other chip select configured for memory address 0 is not considered overlapping of the chip selects. overlapping chip selects refers to configurations where more than one chip select asserts for the same physical address. 5.5 chip select registers the following sections describe the chip select registers.
chip select unit 5-4 5.5.1 upper memory chip select register (umcs, offset a0h) the am186em and am188em microcontrollers provide the ucs chip select pin for the top of memory. on reset, the microcontroller begins fetching and executing instructions starting at memory location ffff0h, so upper memory is usually used as instruction memory. to facilitate this usage, ucs defaults to active on reset with a default memory range of 64 kbytes from f0000h to fffffh, external ready required, and three wait states automatically inserted. the ucs memory range always ends at fffffh. the lower boundary is programmable. the upper memory chip select is configured through the umcs register (figure 5-1). figure 5-1 upper memory chip select register (umcs, offset a0h) the value of the umcs register at reset is f03bh. bit 15: reserved set to 1. bits 14C12: lower boundary (lb2Clb0) the lb2Clb0 bits define the lower bound of the memory accessed through the ucs chip selects. the number of programmable bits has been reduced from eight bits in the 80c186 and 80c188 microcontrollers to three bits in the am186em and am188em microcontrollers. the am186em and am188em microcontrollers provide an additional block size of 512k, which is not available on the 80c186 and 80c188 microcontrollers. table 5-2 outlines the possible configurations and differences with the 80c186 and 80c188 microcontrollers. table 5-2 umcs block size programming values memory block size starting address lb2Clb0 comments 64k f0000h 111b default 128k e0000h 110b 256k c0000h 100b 512k 80000h 000b not available on the 80c186 or 80c188 microcontroller 15 70 lb2Clb0 10000 r1Cr0 0 a19 111 r2 da
chip select unit 5-5 bits 11C8: reserved bit 7: disable address (da) the da bit enables or disables the ad15Cad0 bus during the address phase of a bus cycle when ucs is asserted. if da is set to 1, ad15Cad0 is not driven during the address phase of a bus cycle when ucs is asserted. if da is set to 0, ad15Cad0 is driven during the address phase of a bus cycle. disabling ad15Cad0 reduces power consumption. da defaults to 0 at power-on reset. note: on the am188em microcontroller, the ao15Cao8 address pins are driven during the data phase of the bus cycles, even when the da bit is set to 1 in either the umcs or lmcs register. if bhe /aden (on the am186em) or rfsh 2/aden (on the am188em) is held low on the rising edge of res , then ad15 Cad0 is always driven regardless of the da setting. this configures ad15Cad0 to be enabled regardless of the setting of da. if bhe /aden (on the am186em) or rfsh 2/aden (on the am188em) is high on the rising edge of res , then da in the upper memory chip select (umcs) register and da in the lower memory chip select (lmcs) register control the ad15Cad0 disabling. see the descriptions of the bhe /aden and rfsh 2/aden pins in chapter 3. bits 6: reserved set to 0. bits 5C3: reserved set to 1. bit 2: ready mode (r2) the r2 bit is used to configure the ready mode for the ucs chip select. if r2 is set to 0, external ready is required. if r2 is set to 1, external ready is ignored. in each case, the processor also uses the value of the r1Cr0 bits to determine the number of wait states to insert. r2 defaults to 0 at reset. bits 1C0: wait-state value (r1Cr0) the value of r1Cr0 determines the number of wait states inserted into an access to the ucs memory area. from zero to three wait states can be inserted (r1Cr0 = 00b to 11b). r1Cr0 default to 11b at reset.
chip select unit 5-6 5.5.2 low memory chip select register (lmcs, offset a2h) the am186em and am188em microcontrollers provide the lcs chip select pin for the bottom of memory. since the interrupt vector table is located at 00000h at the bottom of memory, the lcs pin has been provided to facilitate this usage. the lcs pin is not active on reset, but any read or write access to the lmcs register activates this pin. the low memory chip select is configured through the lmcs register (see figure 5-2). figure 5-2 low memory chip select register (lmcs, offset a2h) the value of the lmcs register at reset is undefined. bit 15: reserved set to 0. bits 14C12: upper boundary (ub2Cub0) the ub2Cub0 bits define the upper bound of the memory accessed through the lcs chip select. because of the timing requirements of the lcs output and the nonmultiplexed address bus, the number of programmable memory sizes for the lmcs register is reduced compared to the 80c186 and 80c188 microcontrollers. consequently, the number of programmable bits has been reduced from eight bits in the 80c186 and 80c188 microcontrollers to three bits in the am186em and am188em microcontrollers. the am186em and am188em microcontrollers have a block size of 512 kbytes, which is not available on the 80c186 and 80c188 microcontrollers. table 5-3 outlines the possible configurations and the differences between the 80c186 and 80c188 microcontrollers and the am186em and am188em microcontrollers. table 5-3 lmcs block size programming values memory block size ending address ub2Cub0 comments 64k 0ffffh 000b 128k 1ffffh 001b 256k 3ffffh 011b 512k 7ffffh 111b not available on the 80c186 and 80c188 microcontrollers 1 15 70 0 ub2Cub0 11 1 pse 11 1 a19 r1Cr0 r2 da
chip select unit 5-7 bits 11C8: reserved set to 1. bit 7: disable address (da) the da bit enables or disables the ad15Cad0 bus during the address phase of a bus cycle when lcs is asserted. if da is set to 1, ad15Cad0 is not driven during the address phase of a bus cycle when lcs is asserted. if da is set to 0, ad15Cad0 is driven during the address phase of a bus cycle. disabling ad15Cad0 reduces power consumption. note: on the am188em microcontroller, the ao15Cao8 address pins are driven during the data phase of the bus cycles, even when the da bit is set to 1 in either the upper memory chip select register (umcs) or the low memory chip select register (lmcs). if bhe /aden (on the am186em) or rfsh 2/aden (on the am188em) is held low on the rising edge of res , then ad15 Cad0 is always driven regardless of the da setting. this configures ad15Cad0 to be enabled regardless of the setting of da. if bhe /aden (on the am186em) or rfsh 2/aden (on the am188em) is high on the rising edge of res , then the da bit in the umcs register and the da bit in the lmcs register control the ad15Cad0 disabling. see the descriptions of the bhe /aden and rfsh 2/aden pins in chapter 3. bit 6: psram mode enable (pse) the pse bit is used to enable psram support for the lcs chip select memory space. when pse is set to 1, psram support is enabled. when pse is set to 0, psram support is disabled. the refresh control unit registers edram, mdram, and cdram, must be configured for auto refresh before psram support is enabled. bits 5C3: reserved set to 1. bit 2: ready mode (r2) the r2 bit is used to configure the ready mode for the lcs chip select. if r2 is set to 0, external ready is required. if r2 is set to 1, external ready is ignored. in each case, the processor also uses the value of the r1Cr0 bits to determine the number of wait states to insert. bits 1C0: wait-state value (r1Cr0) the value of r1Cr0 determines the number of wait states inserted into an access to the lcs memory area. from zero to three wait states can be inserted (r1Cr0 =00b to 11b).
chip select unit 5-8 5.5.3 midrange memory chip select register (mmcs, offset a6h) the am186em and am188em microcontrollers provide four chip select pins, mcs 3 Cmcs 0, for use within a user-locatable memory block. the base address of the memory block can be located anywhere within the 1-mbyte memory address space, exclusive of the areas associated with the ucs and lcs chip selects (and, if they are mapped to memory, the address range of the peripheral chip selects, pcs 6Cpcs 5 and pcs 3Cpcs 0). the mcs address range can overlap the pcs address range if the pcs chip selects are mapped to i/o space. the midrange memory chip selects are programmed through two registers. the midrange memory chip select (mmcs) register (see figure 5-3) determines the base address and the ready condition and wait states of the memory block accessed through the mcs pins. the pcs and mcs auxiliary (mpcs) register is used to configure the block size. the mcs 3Cmcs 0 pins are not active on reset. both the mmcs and mpcs registers must be accessed with a read or write to activate these chip selects. unlike the ucs and lcs chip selects, the mcs 3Cmcs 0 outputs assert with the multiplexed ad address bus (ad15Cad0 or ao15Cao8 and ad7Cad0) rather than the earlier timing of the a19Ca0 bus. the a19Ca0 bus can still be used for address selection, but the timing is delayed for a half cycle later than that for ucs and lcs . the midrange memory chip selects are configured by the mmcs register (figure 5-3). figure 5-3 midrange memory chip select register (mmcs, offset a6h) the value of the mmcs register at reset is undefined. bits 15C9: base address (ba19Cba13) the base address of the memory block that is addressed by the mcs chip select pins is determined by the value of ba19Cba13. these bits correspond to bits a19Ca13 of the 20-bit memory address. bits a12Ca0 of the base address are always 0. the base address can be set to any integer multiple of the size of the memory block size selected in the mpcs register. for example, if the midrange block is 32 kbytes, the block could be located at 10000h or 18000h but not at 14000h. the base address of the midrange chip selects can be set to 00000h only if the lcs chip select is not active. this is due to the fact that the lcs base address is defined to be address 00000h and chip select address ranges are not allowed to overlap. because of the additional restriction that the base address must be a multiple of the block size, a 512k mmcs block size can only be used when located at address 00000h, and the lcs chip selects must not be active in this case. use of the mcs chip selects to access low memory allows the timing of these accesses to follow the ad address bus rather than the a address bus. locating a 512k mmcs block at 80000h always conflicts with the range of the ucs chip select and is not allowed. 15 70 ba19Cba13 1 1 1 1 1 1 r1Cr0 r2
chip select unit 5-9 bits 8C3: reserved set to 1. bit 2: ready mode (r2) the r2 bit is used to configure the ready mode for the mcs chip selects. if r2 is set to 0, external ready is required. if r2 is set to 1, external ready is ignored. in each case, the processor also uses the value of the r1Cr0 bits to determine the number of wait states to insert. bits 1C0: wait-state value (r1Cr0) the value of r1Cr0 determines the number of wait states inserted into an access to the mcs memory area. from zero to three wait states can be inserted (r1Cr0 = 00b to 11b).
chip select unit 5-10 5.5.4 pcs and mcs auxiliary register (mpcs, offset a8h) the pcs and mcs auxiliary (mpcs) register (see figure 5-4) differs from the other chip select control registers in that it contains fields that pertain to more than one type of chip select. the mpcs register fields provide program information for mcs 3 Cmcs 0 as well as pcs 6Cpcs 5 and pcs 3Cpcs 0. in addition to its function as a chip select control register, the mpcs register contains a field that configures the pcs 6Cpcs 5 pins as either chip selects or as alternate sources for the a2 and a1 address bits. when programmed to provide address bits a1 and a2, pcs 6C pcs 5 cannot be used as peripheral chip selects. these outputs can be used to provide latched address bits for a2 and a1. on reset, pcs 6Cpcs 5 are not active. if pcs 6Cpcs 5 are configured as address pins, an access to the mpcs register causes the pins to activate. no corresponding access to the pacs register is required to activate the pcs 6Cpcs 5 pins as addresses. figure 5-4 pcs and mcs auxiliary register (mpcs, offset a8h) the value of the mpcs register at reset is undefined. bit 15: reserved set to 1. bits 14C8: mcs block size (m6Cm0) this field determines the total block size for the mcs 3Cmcs 0 chip selects. each individual chip select is active for one quarter of the total block size. the size of the memory block defined is shown in table 5-4. only one of the m6Cm0 bits can be set at any time. if more than one of the m6Cm0 bits is set, unpredictable operation of the mcs lines occurs. table 5-4 mcs block size programming total block size individual select size m6Cm0 8k 2k 0000001b 16k 4k 0000010b 32k 8k 0000100b 64k 16k 0001000b 128k 32k 0010000b 256k 64k 0100000b 512k 128k 1000000b 15 70 ms ex m6Cm0 1 11 1 r1Cr0 r2
chip select unit 5-11 bit 7: pin selector (ex) this bit determines whether the pcs 6Cpcs 5 pins are configured as chip selects or as alternate outputs for a2Ca1. when this bit is set to 1, pcs 6Cpcs 5 are configured as peripheral chip select pins. when ex is set to 0, pcs 5 becomes address bit a1 and pcs 6 becomes address bit a2. bit 6: memory/ i/o space selector (ms) this bit determines whether the pcs pins are active during memory bus cycles or i/o bus cycles. when ms is set to 1, the pcs outputs are active for memory bus cycles. when ms is set to 0, the pcs outputs are active for i/o bus cycles. bits 5C3: reserved set to 1. bit 2: ready mode (r2) this bit applies only to the pcs 6Cpcs 5 chip selects. if r2 is set to 0, external ready is required. if r2 is set to 1, external ready is ignored. in each case, the processor also uses the value of the r1Cr0 bits to determine the number of wait states to insert. bits 1C0: wait-state value (r1Cr0) these bits apply only to the pcs 6Cpcs 5 chip selects. the value of r1Cr0 determines the number of wait states inserted into an access to the pcs memory or i/o area. from zero to three wait states can be inserted (r1Cr0 = 00b to 11b).
chip select unit 5-12 5.5.5 peripheral chip select register (pacs, offset a4h) unlike the ucs and lcs chip selects, the pcs outputs assert with the same timing as the multiplexed ad address bus. also, each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. the am186em and am188em microcontrollers provide six chip selects, pcs 6 Cpcs 5 and pcs 3Cpcs 0, for use within a user-locatable memory or i/o block. (pcs 4 is not implemented on the am186em and am 188em microcontrollers.) the base address of the memory block can be located anywhere within the 1-mbyte memory address space, exclusive of the areas associated with the ucs , lcs , and mcs chip selects, or they can be configured to access the 64-kbyte i/o space. the peripheral chip selects are programmed through two registersthe peripheral chip select (pacs) register and the pcs and mcs auxiliary (mpcs) register. the peripheral chip select (pacs) register (figure 5-5) determines the base address, the ready condition, and the wait states for the pcs 3Cpcs 0 outputs. the pcs and mcs auxiliary (mpcs) register (see figure 5-4) contains bits that configure the pcs 6Cpcs 5 pins as either chip selects or address pins a1 and a2. when the pcs 6C pcs 5 pins are chip selects, the mpcs register also determines whether pcs chip selects are active during memory or i/o bus cycles and specifies the ready and wait states for the pcs 6Cpcs 5 outputs. the pcs pins are not active on reset. both the pacs and mpcs registers must be accessed with a read or write to activate the pcs pins as chip selects. pcs 6Cpcs 5 can be configured and activated as address pins by writing only the mpcs register. no corresponding access to the pacs register is required in this case. pcs 3Cpcs 0 can be configured for zero wait states to 15 wait states. pcs 6Cpcs 5 can be configured for zero wait states to three wait states. figure 5-5 peripheral chip select register (pacs, offset a4h) the value of the pacs register at reset is undefined. bits 15C7: base address (ba19Cba11) the base address of the peripheral chip select block is defined by ba19Cba11 of the pacs register. ba19Cba11 correspond to bits 19C11 of the 20-bit programmable base address of the peripheral chip select block. bit 6 of the pacs register corresponds to bit 10 of the base address in the 80c186 and 80c188 microcontrollers, and is not implemented. thus, code previously written for the 80c186 microcontroller in which bit 6 was set with a meaningful value would not produce the address expected on the am186em. when the pcs chip selects are mapped to i/o space, ba19C16 must be programmed to 0000b because the i/o address bus is only 16-bits wide. 15 70 ba19Cba11 1 1 1 r1Cr0 r2 r3
chip select unit 5-13 table 5-5 pcs address ranges bits 6C4: reserved set to 1. bit 3: wait-state value (r3) if this bit is set to 0, the number of wait states from zero to three is encoded in the r1Cr0 bits. in this case, r1Cr0 encodes from zero (00b) to three (11b) wait states. when r3 is set to 1, the four possible values of r1Cr0 encode four additional wait-state values as follows: 00b = 5 wait states, 01b = 7 wait states, 10b = 9 wait states, and 11b = 15 wait states. table 5-6 shows the wait-state encoding. table 5-6 pcs 3Cpcs 0 wait-state encoding bit 2: ready mode (r2) the r2 bit is used to configure the ready mode for the pcs 3C pcs 0 chip selects. if r2 is set to 0, external ready is required. external ready is ignored when r2 is set to 1. in each case, the processor also uses the value of the r3 and r1Cr0 bits to determine the number of wait states to insert. the ready mode for pcs 6Cpcs 5 is configured through the mpcs register. bits 1C0: wait-state value (r1Cr0) the value of r3 and r1Cr0 determines the number of wait states inserted into a pcs 3Cpcs 0 access. up to 15 wait states can be inserted. see the discussion of bit 3 (r3) for the wait-state encoding of r1Cr0. from zero to three wait states for the pcs 6Cpcs 5 outputs are programmed through the r1Cr0 bits in the mpcs register. pcs line range low high pcs 0 base address base address+255 pcs 1 base address+256 base address+511 pcs 2 base address+512 base address+767 pcs 3 base address+768 base address+1023 reserved n/a n/a pcs 5 base address+1280 base address+1535 pcs 6 base address+1536 base address+1791 r3 r1 r0 wait states 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 5 1 0 1 7 1 1 0 9 1 1 1 15
chip select unit 5-14
refresh control unit 6-1 chapter 6 refresh control unit 6.1 overview the refresh control unit (rcu) automatically generates refresh bus cycles. after a programmable period of time, the rcu generates a memory read request to the bus interface unit. the rcu is fixed to three wait states for the psram auto refresh mode. the refresh control unit operates off the processor internal clock. if the power-save mode is in effect, the refresh control unit must be reprogrammed to reflect the new clock rate. if the hlda pin is active when a refresh request is generated (indicating a bus hold condition), then the microcontroller deactivates the hlda pin in order to perform a refresh cycle. the circuit external bus master must remove the hold signal for at least one clock to allow the refresh cycle to execute. 6.1.1 memory partition register (mdram, offset e0h) figure 6-1 memory partition register (mdram, offset e0h) the mdram register is set to 0000h on reset. bits 15C9: refresh base (m6Cm0) upper bits corresponding to address bits a19Ca13 of the 20-bit memory refresh address. since these bits are available only on the ad bus, the ad bit must not be set in the lmcs register if the refresh control unit is used. when using psram mode, m6Cm0 must be programmed to 0000000b. these bits are cleared to 0 at reset. bits 8C0: reserved read back as 0. 15 70 m6Cm0 ra19 ra13 00000000 0
refresh control unit 6-2 6.1.2 clock prescaler register (cdram, offset e2h) figure 6-2 clock prescaler register (cdram, offset e2h) the cdram register is undefined on reset. bits 15C9: reserved read back as 0. bits 8C0: refresh counter reload value (rc8Crc0) contains the value of the desired clock count interval between refresh cycles. the counter value should not be set to less than 18 (12h), otherwise there would never be sufficient bus cycles available for the processor to execute code. in power-save mode, the refresh counter value must be adjusted to take into account the reduced processor clock rate. 6.1.3 enable rcu register (edram, offset e4h) figure 6-3 enable rcu register (edram, offset e4h) the edram register is set to 0000h on reset. bit 15: enable rcu (e) enables the refresh counter unit when set to 1. clearing the e bit at any time clears the refresh counter and stops refresh requests, but it does not reset the refresh address. set to 0 on reset. bits 14C9: reserved read back as 0. bits 8C0: refresh count (t8Ct0) this read-only field contains the present value of the down counter which triggers refresh requests. 15 70 00000 0 rc8Crc0 0 15 70 00000 t8Ct0 0 e
interrupt control unit 7-1 chapter 7 interrupt control unit 7.1 overview the am186em and am188em microcontrollers can receive interrupt requests from a variety of sources, both internal and external. the internal interrupt controller arranges these requests by priority and presents them one at a time to the cpu. there are six external interrupt sources on the am186em and am188em microcontrollers five maskable interrupt pins (int4Cint0) and the non-maskable interrupt (nmi) pin. there are six internal interrupt sources that are not connected to external pinsthree timers, two dma channels, and the asynchronous serial port. the am186em and am188em microcontrollers provide three interrupts that are not present on the 80c186 and 80c188 microcontrollers: n int4, an additional external interrupt pin that operates like the int3Cint0 pins n an internal watchdog timer interrupt n an internal interrupt from the serial port the int4Cint0 interrupt request pins can be used as direct interrupt requests. if more inputs are needed, int3Cint0 can also be cascaded with an 82c59a-compatible external interrupt control device. an external interrupt controller can be used as the system master by programming the internal interrupt controller to operate in slave mode. in all cases, nesting can be enabled that allows high priority interrupts to interrupt lower-priority interrupt service routines. 7.1.1 definitions of interrupt terms the following definitions cover some of the terminology that is used in describing the functionality of the interrupt controller. table 7-1 contains information regarding the reserved interrupts. 7.1.1.1 interrupt type an 8-bit interrupt type identifies each of the 256 possible interrupts. software exceptions, internal peripherals, and non-cascaded external interrupts supply the interrupt type through the internal interrupt controller. cascaded external interrupts and slave-mode external interrupts get the interrupt type from the external interrupt controller by means of interrupt acknowledge cycles on the bus.
interrupt control unit 7-2 7.1.1.2 interrupt vector table the interrupt vector table is a memory area of 1 kbyte beginning at address 00000h that holds up to 256 four-byte address pointers containing the address for the interrupt service routine for each possible interrupt type. for each interrupt, an 8-bit interrupt type identifies the appropriate interrupt vector table entry. interrupts 00h to 1fh are reserved. see table 7-1. the processor calculates the index to the interrupt vector table by shifting the interrupt type left 2 bits (multiplying by 4). 7.1.1.3 maskable and non-maskable interrupts interrupt types 08h through 1fh are maskable. of these, only 08h through 14h are actually in use (see table 7-1). the maskable interrupts are enabled and disabled by the interrupt enable flag (if) in the processor status flags, but the int command can execute any interrupt regardless of the setting of if. interrupt types 00h through 07h and all software interrupts (the int instruction) are non- maskable. the non-maskable interrupts are not affected by the setting of the if flag. the am186em and am188em microcontrollers provide two methods for masking and unmasking the maskable interrupt sources. each interrupt source has an interrupt control register that contains a mask bit specific to that interrupt. in addition, the interrupt mask register is provided as a single source to access all of the mask bits. if the interrupt mask register is written while interrupts are enabled, it is possible that an interrupt could occur while the register is in an undefined state. this can cause interrupts to be accepted even though they were masked both before and after the write to the interrupt mask register. therefore, the interrupt mask register should only be written when interrupts are disabled. mask bits in the individual interrupt control registers can be written while interrupts are enabled, and there will be no erroneous interrupt operation. 7.1.1.4 interrupt enable flag (if) the interrupt enable flag (if) is part of the processor status flags (see section 2.1.1 on page 2-2). if if is set to 1, maskable interrupts are enabled and can cause processor interrupts. (individual maskable interrupts can still be disabled by means of the mask bit in each control register.) if if is set to 0, all maskable interrupts are disabled. the if flag does not affect the nmi or software exception interrupts (interrupt types 00h to 07h), and it does not affect the execution of any interrupt through the int instruction. 7.1.1.5 interrupt mask bit each of the interrupt control registers for the maskable interrupts contains a mask bit (msk). if msk is set to 1 for a particular interrupt, that interrupt is disabled regardless of the if setting. 7.1.1.6 interrupt priority the column titled overall priority in table 7-1 shows the fundamental priority breakdown for the interrupts at power-on reset. the non-maskable interrupts 00h through 07h are always prioritized ahead of the maskable interrupts. the maskable interrupts can be reprioritized by reconfiguring the pr2Cpr0 bits in the interrupt control registers. the pr2Cpr0 bits in all the maskable interrupts are set to priority level 7 at power-on reset.
interrupt control unit 7-3 7.1.1.7 software interrupts software interrupts can be initiated by the int instruction. any of the 256 possible interrupts can be initiated by the int instruction. int 21h causes an interrupt to the vector located at 00084h in the interrupt vector table. int ffh causes an interrupt to the vector located at 003fch in the interrupt vector table. software interrupts are not maskable and are not affected by the setting of the if flag. 7.1.1.8 software exceptions a software exception interrupt occurs when an instruction causes an interrupt due to some condition in the processor. interrupt types 00h, 01h, 03h, 04h, 05h, 06h, and 07h are software exception interrupts. software exceptions are not maskable and are not affected by the setting of the if flag. table 7-1 am186em and am188em microcontroller interrupt types notes: 1. interrupts generated as a result of an instruction execution. 2. trace is performed in the same manner as 80c186 and 80c188. 3. an esc opcode causes a trap. this is part of the 80c186 and 80c188 co-processor interface, which is not supported on the am186em. 4. all three timers constitute one source of request to the interrupt controller. as such, they share the same priority level with respect to other interrupt sources. however, the timers have a defined priority order among themselves (2a>2b >2c). 5. the interrupt types of these sources are programmable in slave mode. 6. not available in slave mode. interrupt name interrupt type vector table address eoi type overall priority related instructions notes divide error exception 00h 00h n/a 1 div, idiv 1 trace interrupt 01h 04h n/a 1a all 2 non-maskable interrupt (nmi) 02h 08h n/a 1b breakpoint interrupt 03h 0ch n/a 1 int 3 1 into detected overflow exception 04h 10h n/a 1 into 1 array bounds exception 05h 14h n/a 1 bound 1 unused opcode exception 06h 18h n/a 1 undefined opcodes 1 esc opcode exception 07h 1ch n/a 1 esc opcodes 1, 3 timer 0 interrupt 08h 20h 08 2a 4, 5 timer 1 interrupt 12h 48h 08 2b 4, 5 timer 2 interrupt 13h 4ch 08 2c 4, 5 reserved for amd use 09h dma 0 interrupt 0ah 28h 0a 3 5 dma 1 interrupt 0bh 2ch 0b 4 5 int0 interrupt 0ch 30h 0c 5 int1 interrupt 0dh 34h 0d 6 int2 interrupt 0eh 38h 0e 7 int3 interrupt 0fh 3ch 0f 8 int4 interrupt 10h 40h 10 9 6 watchdog timer interrupt 11h 44h 11 9 6 asynchronous serial port interrupt 14h 50h 14 9 6 reserved for amd use 15hC1fh
interrupt control unit 7-4 7.1.2 interrupt conditions and sequence interrupts are generally serviced as follows. 7.1.2.1 non-maskable interrupts non-maskable interruptsthe trace interrupt, the nmi interrupt, and software interrupts [both user-defined (int) and software exceptions]are serviced regardless of the setting of the interrupt enable flag (if) in the processor status flags. 7.1.2.2 maskable hardware interrupts in order for maskable hardware interrupt requests to be serviced, the if flag must be set by the sti instruction, and the mask bit associated with each interrupt must be reset. 7.1.2.3 the interrupt request when an interrupt is requested, the internal interrupt controller verifies that the interrupt is enabled and that there are no higher priority interrupt requests being serviced or pending. if the interrupt request is granted, the interrupt controller uses the interrupt type (see table 7-1) to access a vector from the interrupt vector table. each interrupt type has a four-byte vector available in the interrupt vector table. the interrupt vector table is located in the 1024 bytes from 00000h to 003ffh. each four-byte vector consists of a 16-bit offset (ip) value and a 16-bit segment (cs) value. the 8-bit interrupt type is shifted left 2 bit positions (multiplied by 4) to generate the index into the interrupt vector table. 7.1.2.4 interrupt servicing a valid interrupt transfers execution to a new program location based on the vector in the interrupt vector table. the next instruction address (cs:ip) and the processor status flags are pushed onto the stack. the interrupt enable flag (if) is cleared after the processor status flags are pushed on the stack, disabling maskable interrupts during the interrupt service routine (isr). the segment:offset values from the interrupt vector table are loaded into the code segment (cs) and the instruction pointer (ip), and execution of the isr begins. 7.1.2.5 returning from the interrupt the interrupt return (iret) instruction pops the processor status flags and the return address off the stack. program execution resumes at the point where the interrupt occurred. the interrupt enable flag (if) is restored by the iret instruction along with the rest of the processor status flags. if the if flag was set before the interrupt was serviced, interrupts are re-enabled when the iret is executed. if there are valid interrupts pending when the iret is executed, the instruction at the return address is not executed. instead, the new interrupt is serviced immediately. if an isr intends to permanently modify the value of any of the saved flags, it must modify the copy of the processor status flags register that was pushed onto the stack.
interrupt control unit 7-5 7.1.3 interrupt priority table 7-1 shows the predefined types and overall priority structure for the am186em and am188em microcontrollers. non-maskable interrupts (interrupt types 0C7) are always higher priority than maskable interrupts. maskable interrupts have a programmable priority that can override the default priorities relative to one another. the levels of interrupt priority are as follows: n interrupt priority for non-maskable interrupts and software interrupts n interrupt priority for maskable hardware interrupts 7.1.3.1 non-maskable interrupts and software interrupt priority the non-maskable interrupts from 00h to 07h and software interrupts (int instruction) always take priority over the maskable hardware interrupts. within the non-maskable and software interrupts, the trace interrupt has the highest priority, followed by the nmi interrupt, followed by the remaining non-maskable and software interrupts. after the trace interrupt and the nmi interrupt, the remaining software exceptions are mutually exclusive and can only occur one at a time, so there is no further priority breakdown. 7.1.3.2 maskable hardware interrupt priority beginning with interrupt type 8 (the timer 0 interrupt), the maskable hardware interrupts have both an overall priority (see table 7-1) and a programmable priority. the programmable priority is the primary priority for maskable hardware interrupts. the overall priority is the secondary priority for maskable hardware interrupts. since all maskable interrupts are set to a programmable priority of seven on reset, the overall priority of the interrupts determines the priority in which each interrupt is granted by the interrupt controller until programmable priorities are changed by reconfiguring the control registers. the overall priority levels shown in table 7-1 are not the same as the programmable priority level that is associated with each maskable hardware interrupt. each of the maskable hardware interrupts has a programmable priority from zero to seven, with zero being the highest priority (see table 7-3 on page 7-14). for example, if the int4Cint0 interrupts are all changed to programmable priority six and no other programmable priorities are changed from the reset value of seven, then the int4C int0 interrupts take precedence over all other maskable interrupts. (within int4Cint0, int0 takes precedence over int1, and int1 takes precedence over int2, etc., because of the underlying hierarchy of the overall priority.)
interrupt control unit 7-6 7.1.4 software exceptions, traps, and nmi the following predefined interrupts cannot be masked by programming. 7.1.4.1 divide error exception (interrupt type 00h) generated when a div or idiv instruction quotient cannot be expressed in the number of destination bits. 7.1.4.2 trace interrupt (interrupt type 01h) if the trace flag (tf) in the processor status flags register is set, the trace interrupt is generated after most instructions. this interrupt allows programs to execute in single-step mode. the interrupt is not generated after prefix instructions like rep, instructions that modify segment registers like pop ds, or the wait instruction. taking the trace interrupt clears the tf bit after the processor status flags are pushed onto the stack. the iret instruction at the end of the single step interrupt service routine restores the processor status flags (and the tf bit) and transfers control to the next instruction to be traced. trace mode is initiated by pushing the processor status flags onto the stack, setting the tf flag on the stack, and then popping the flags. 7.1.4.3 non-maskable interruptnmi (interrupt type 02h) the nmi pin provides an external interrupt source that is serviced regardless of the state of the if (interrupt enable flag) bit. no external interrupt acknowledge sequence is performed for an nmi interrupt (see section 7.1.5). a typical use of nmi is to activate a power failure routine. 7.1.4.4 breakpoint interrupt (interrupt type 03h) an interrupt caused by the 1-byte version of the int instruction (int3). 7.1.4.5 into detected overflow exception (interrupt type 04h) generated by an into instruction if the of bit is set in the processor status flags (flags) register. 7.1.4.6 array bounds exception (interrupt type 05h) generated by a bound instruction if the array index is outside the array bounds. the array bounds are located in memory at a location indicated by one of the instruction operands. the other operand indicates the value of the index to be checked. 7.1.4.7 unused opcode exception (interrupt type 06h) generated if execution is attempted on undefined opcodes. 7.1.4.8 esc opcode exception (interrupt type 07h) generated if execution of esc opcodes (d8hCdfh) is attempted. the microcontrollers do not check the escape opcode trap bit. the return address of this exception points to the esc instruction that caused the exception. if a segment override prefix preceded the esc instruction, the return address points to the segment override prefix. note: all numeric coprocessor opcodes cause a trap. the am186em and am188em microcontrollers do not support the numeric coprocessor interface.
interrupt control unit 7-7 7.1.5 interrupt acknowledge interrupts can be acknowledged in two different waysthe internal interrupt controller can provide the interrupt type or an external interrupt controller can provide the interrupt type. the processor requires the interrupt type as an index into the interrupt vector table. when the internal interrupt controller is supplying the interrupt type, no bus cycles are generated. the only external indication that an interrupt is being serviced is the processor reading the interrupt vector table. when an external interrupt controller is supplying the interrupt type, the processor generates two interrupt acknowledge bus cycles (see figure 7-1). the interrupt type is written to the ad7Cad0 lines by the external interrupt controller during the second bus cycle. interrupt acknowledge bus cycles have the following characteristics: n the two interrupt acknowledge cycles are internally locked. (there is no lock pin on the am186em and am188em microcontrollers.) n two idle states are always inserted between the two cycles. n wait states are inserted if ready is not returned to the processor. figure 7-1 external interrupt acknowledge bus cycles notes: 1. ale is active for each inta cycle. 2. rd is inactive. t1 t2 t3 t4 t1 t2 t3 t4 s 0Cs 2 inta internal lock ti ti interrupt acknowledge interrupt acknowledge ad7Cad0 interrupt type
interrupt control unit 7-8 7.1.6 interrupt controller reset conditions on reset, the interrupt controller performs the following nine actions: 1. all special fully nested mode (sfnm) bits are reset, implying fully nested mode. 2. all priority (pr) bits in the various control registers are set to 1. this places all sources at the lowest priority (level 7). 3. all level-triggered mode (ltm) bits are reset to 0, resulting in edge-triggered mode. 4. all interrupt in-service bits are reset to 0. 5. all interrupt request bits are reset to 0. 6. all mask (msk) bits are set to 1. all interrupts are masked. 7. all cascade (c) bits are reset to 0 (non-cascade). 8. the interrupt priority mask is set to 7, allowing interrupts of all priorities. 9. the interrupt controller is initialized to master mode.
interrupt control unit 7-9 7.2 master mode operation this section describes master mode operation of the internal interrupt controller. see section 7.4 on page 7-28 for a description of slave mode operation. six pins are provided for external interrupt sources. one of these pins is nmi, the non- maskable interrupt. nmi is generally used for unusual events like power failure. the other five pins can be configured in any of the following ways: n fully nested modefive interrupt lines with internally-generated interrupt types n cascade mode onean interrupt line and interrupt acknowledge line pair with externally- generated interrupt types, plus three interrupt input lines with internally-generated types n cascade mode twotwo pairs of interrupt and interrupt acknowledge lines with externally-generated interrupt types, and one interrupt input line (int4) with internally- generated type the basic modes of operation of the interrupt controller in master mode are similar to the 82c59a. the interrupt controller responds identically to internal interrupts in all three modes, the difference is only in the interpretation of function of the five external interrupt pins. the interrupt controller is set into one of these modes by programming the correct bits in the int0 and int1 control registers. the modes of interrupt controller operation are fully nested mode, cascade mode, special fully nested mode, and polled mode. 7.2.1 fully nested mode in fully nested mode, five pins are used as direct interrupt requests as in figure 7-2. the interrupt types for these five inputs are generated internally. an in-service bit is provided for every interrupt source. if a lower-priority device requests an interrupt while the in-service bit (is) is set for a higher priority interrupt, no interrupt is generated by the interrupt controller. in addition, if another interrupt request occurs from the same interrupt source while the in- service bit is set, no interrupt is generated by the interrupt controller. this allows interrupt service routines operating with interrupts enabled to be suspended only by interrupts of equal or higher priority than the in-service interrupt. when an interrupt service routine is completed, the proper is bit must be reset by writing the interrupt type to the eoi register. this is required to allow subsequent interrupts from this interrupt source and to allow servicing of lower-priority interrupts. a write to the eoi register should be executed at the end of the interrupt service routine just before the return from interrupt instruction. figure 7-2 fully nested (direct) mode interrupt controller connections am186em or am188em microcontroller int1 int3 interrupt source interrupt source interrupt source interrupt source int2 int0 int4 interrupt source
interrupt control unit 7-10 7.2.2 cascade mode the am186em and am188em microcontrollers have five interrupt pins, two of which (int2 and int3) have dual functions. in fully nested mode, the five pins are used as direct interrupt inputs and the corresponding interrupt types are generated internally. in cascade mode, four of the five pins can be configured into interrupt input and dedicated acknowledge signal pairs. int0 can be configured with interrupt acknowledge inta 0 (int2). int1 can be configured with interrupt acknowledge inta 1 (int3). external sources in cascade mode use externally generated interrupt types. when an interrupt is acknowledged, two inta cycles are initiated and the type is read into the microcontroller on the second cycle (see section 7.1.5 on page 7-7). the capability to interface to one or two external 82c59a programmable interrupt controllers is provided when the inputs are configured in cascade mode. figure 7-3 shows the interconnection for cascade mode. int0 is an interrupt input interfaced to one 82c59a, and int2/inta 0 serves as the dedicated interrupt acknowledge signal to that peripheral. int1 and int3/inta 1 are also interfaced to an 82c59a. each interrupt and acknowledge pair can be selectively placed in the cascade or non-cascade mode by programming the proper value into the int0 and int1 control registers. the dedicated acknowledge signals eliminate the need for external logic to generate inta and device select signals. cascade mode provides the capability to serve up to 128 external interrupt sources through the use of external master and slave 82c59as. three levels of priority are created, requiring priority resolution in the microcontroller interrupt controller, the master 82c59as, and the slave 82c59as. if an external interrupt is serviced, one is bit is set at each of these levels. when the interrupt service routine is completed, up to three end-of-interrupt (eoi) register writes must be issued by the program. figure 7-3 cascade mode interrupt controller connections am186em or am188em microcontroller 82c59a int0 v cc 82c59a v cc int1 82c59a 82c59a interrupt sources interrupt sources inta 0 inta 1 int4
interrupt control unit 7-11 7.2.3 special fully nested mode specially fully nested mode is entered by setting the sfnm bit in the int0 or int1 control registers. (see section 7.3.1 on page 7-13.) it enables complete nesting with external 82c59a masters or multiple interrupts from the same external interrupt pin when not in cascade mode. in this case, the isrs must be re-entrant. in fully nested mode, an interrupt request from an interrupt source is not recognized when the in-service bit for that source is set. in this case, if more than one interrupt source is connected to an external interrupt controller, all of the interrupts go through the same am186em or am188em microcontroller interrupt request pin. as a result, if the external interrupt controller receives a higher-priority interrupt, its interrupt is not recognized by the microcontroller until the in-service bit is reset. in special fully nested mode, the microcontrollers interrupt controller allows the processor to take interrupts from an external pin regardless of the state of the in-service bit for an interrupt source in order to allow multiple interrupts from a single pin. an in-service bit continues to be set, however, to inhibit interrupts from other lower-priority am186em or am188em microcontroller interrupt sources. in special fully nested mode with cascade mode, when a write is issued to the eoi register at the end of the interrupt service routine, software polling of the is register in the external master 82c59a must determine if there is more than one is bit set. if so, the is bit in the microcontroller remains active and the next isr is entered. 7.2.4 operation in a polled environment to allow reading of the poll register information without setting the indicated in-service bit, the am186em and am188em microcontrollers provide a poll status register (figure 7-15) in addition to the poll register. poll register information is duplicated in the poll status register, but the poll status register can be read without setting the associated in-service bit. these registers are located in two adjacent memory locations in the peripheral control block. the interrupt controller can be used in polled mode if interrupts are not desired. when polling, interrupts are disabled and software polls the interrupt controller as required. the interrupt controller is polled by reading the poll status register (figure 7-15). bit 15 in the poll status register indicates to the processor that an interrupt of high enough priority is requesting service. bits 4C0 indicate to the processor the interrupt type of the highest priority source requesting service. after determining that an interrupt is pending, software reads the poll register (rather than the poll status register), which causes the in-service bit of the highest priority source to be set. 7.2.5 end-of-interrupt write to the eoi register a program must write to the eoi register to reset the in-service (is) bit when an interrupt service routine is completed. there are two types of writes to the eoi registerspecific eoi and non-specific eoi (see section 7.3.14 on page 7-27). non-specific eoi does not specify which is bit is to be reset. instead, the interrupt controller automatically resets the is bit of the highest priority source with an active service routine. specific eoi requires the program to send the interrupt type to the interrupt controller to indicate the source is bit that is to be reset. specific reset is applicable when interrupt nesting is possible or when the highest priority is bit that was set does not belong to the service routine in progress.
interrupt control unit 7-12 7.3 master mode interrupt controller registers the interrupt controller registers for master mode are shown in table 7-2. all the registers can be read and written unless otherwise specified. registers can be redefined in slave mode. see section 7.4 on page 7-28 for detailed information regarding slave mode register usage. on reset, the microcontroller is in master mode. bit 14 of the relocation register (see figure 4-2) must be set to initiate slave mode operation. table 7-2 interrupt controller registers in master mode offset register mnemonic register name associated pins comments 3ah i1con int1 control int1 38h i0con int0 control int0 3eh i3con int3 control int3 3ch i2con int2 control int2 40h i4con int4 control int4 36h dma1con dma1 interrupt control drq1 34h dma0con dma0 interrupt control drq0 32h tcucon timer interrupt control tmrin1 tmrin0 tmrout1 tmrout0 42h wdcon watchdog timer interrupt control 44h spicon serial port interrupt control txd, rxd 30h intsts interrupt status 2eh reqst interrupt request int4Cint0 drq1Cdrq0 read-only register 2ch inserv in-service int4Cint0 drq1Cdrq0 2ah primsk priority mask 28h imask interrupt mask int4Cint0 drq1Cdrq0 26h pollst poll status read-only register 24h poll poll read-only register 22h eoi end of interrupt write-only register
interrupt control unit 7-13 7.3.1 int0 and int1 control registers (i0con, offset 38h, i1con, offset 3ah) (master mode) the int0 interrupt is assigned to interrupt type 0ch. the int1 interrupt is assigned to interrupt type 0dh. when cascade mode is enabled for int0 by setting the c bit of i0con to 1, the int2 pin becomes inta 0, the interrupt acknowledge for int0. when cascade mode is enabled for int1 by setting the c bit of i1con to 1, the int3 pin becomes inta 1, the interrupt acknowledge for int1. figure 7-4 int0 and int1 control registers (i0con, i1con, offsets 38h and 3ah) the value of i0con and i1con at reset is 000fh. bits 15C7: reserved set to 0. bit 6: special fully nested mode (sfnm) when set to 1, enables special fully nested mode. bit 5: cascade mode (c) when set to 1, this bit enables cascade mode. bit 4: level-triggered mode (ltm) this bit determines whether the microcontroller interprets an int0 or int1 interrupt request as edge- or level-sensitive. a 1 in this bit configures int0 or int1 as an active high, level-sensitive interrupt. a 0 in this bit configures int0 or int1 as a low-to-high, edge-triggered interrupt. in either case, int0 or int1 must remain high until they are acknowledged. bit 3: mask (msk) this bit determines whether the int0 or int1 signal can cause an interrupt. a 1 in this bit masks this interrupt source, preventing int0 or int1 from causing an interrupt. a 0 in this bit enables int0 or int1 interrupts. this bit is duplicated in the interrupt mask register. see the interrupt mask register in section 7.3.11 on page 7-24. bits 2C0: priority level (pr2Cpr0) this field determines the priority of int0 or int1 relative to the other interrupt signals, as shown in table 7-3 on page 7-14. 15 70 reserved pr2 pr1 pr0 msk ltm c sfnm
interrupt control unit 7-14 table 7-3 priority level priority pr2Cpr0 (high) 0 0 0 0b 1 0 0 1b 2 0 1 0b 3 0 1 1b 4 1 0 0b 5 1 0 1b 6 1 1 0b (low) 7 1 1 1b
interrupt control unit 7-15 7.3.2 int2 and int3 control registers (i2con, offset 3ch, i3con, offset 3eh) (master mode) the int2 interrupt is assigned to interrupt type oeh. the int3 interrupt is assigned to interrupt type 0fh. the int2 and int3 pins can be configured as interrupt acknowledge pins inta 0 and inta 1 when cascade mode is implemented. figure 7-5 int2 and int3 control registers (i2con, i3con, offsets 3ch and 3eh) the value of i2con and i3con at reset is 000fh. bits 15C5: reserved set to 0. bit 4: level-triggered mode (ltm) this bit determines whether the microcontroller interprets an int2 or int3 interrupt request as edge- or level-sensitive. a 1 in this bit configures int2 or int3 as an active high, level-sensitive interrupt. a 0 in this bit configures int2 or int3 as a low-to-high, edge-triggered interrupt. in either case, int2 or int3 must remain high until they are acknowledged. bit 3: mask (msk) this bit determines whether the int2 or int3 signal can cause an interrupt. a 1 in this bit masks this interrupt source, preventing int2 or int3 from causing an interrupt. a 0 in this bit enables int2 or int3 interrupts. this bit is duplicated in the interrupt mask register. see the interrupt mask register in section 7.3.11 on page 7-24. bits 2C0: priority level (pr2Cpr0) this field determines the priority of int2 or int3 relative to the other interrupt signals, as shown in table 7-3 on page 7-14. 15 70 reserved pr2 pr1 pr0 msk ltm
interrupt control unit 7-16 7.3.3 int4 control register (i4con, offset 40h) (master mode) the am186em and am188em microcontrollers provide int4, an additional external interrupt pin. this input behaves like int3Cint0 on the 80c186/188 microcontroller with the exception that int4 is only intended for use as a nested-mode interrupt source. this interrupt is assigned to interrupt type 10h. the interrupt 4 control register (see figure 7-6) controls the operation of the int4 signal. figure 7-6 int4 control register (i4con, offset 40h) the value of i4con at reset is 000fh. bits 15C5: reserved set to 0. bit 4: level-triggered mode (ltm) this bit determines whether the microcontroller interprets an int4 interrupt request as edge- or level-sensitive. a 1 in this bit configures int4 as an active high, level-sensitive interrupt. a 0 in this bit configures int4 as a low- to-high, edge-triggered interrupt. in either case, int4 must remain high until it is acknowledged. bit 3: mask (msk) this bit determines whether the int4 signal can cause an interrupt. a 1 in this bit masks this interrupt source, preventing int4 from causing an interrupt. a 0 in this bit enables int4 interrupts. this bit is duplicated in the interrupt mask register. see the interrupt mask register in section 7.3.11 on page 7-24. bits 2C0: priority (pr) this field determines the priority of int4 relative to the other interrupt signals, as shown in table 7-3 on page 7-14. 15 70 msk ltm reserved pr2 pr1 pr0
interrupt control unit 7-17 7.3.4 timer and dma interrupt control registers (tcucon, offset 32h, dma0con, offset 34h, dma1con, offset 36h) (master mode) the three timer interrupts are assigned to interrupt type 08h, 12h, and 13h. all three timer interrupts are configured through tcucon, offset 32h. the dma0 interrupt is assigned to interrupt type 0ah. the dma1 interrupt is assigned to interrupt type 0bh. figure 7-7 timer/dma interrupt control registers (tcucon, dma0con, dma1con, offsets 32h, 34h, and 36h) the value of tcucon, dma0con, and dma1con at reset is 000fh. bits 15C4: reserved set to 0. bit 3: interrupt mask (msk) this bit determines whether the corresponding signal can generate an interrupt. a 1 masks this interrupt source. a 0 enables the corresponding interrupt. this bit is duplicated in the interrupt mask register. see the interrupt mask register in section 7.3.11 on page 7-24. bits 2C0: priority level (pr2Cpr0) sets the priority level for its corresponding source. see table 7-3 on page 7-14. 15 70 000 000 00 0 000 pr2 pr1 pr0 msk
interrupt control unit 7-18 7.3.5 watchdog timer interrupt control register (wdcon, offset 42h) (master mode) the am186em and am188em microcontrollers provide an additional on-chip interrupt source, the watchdog timer. this timer is constructed from existing 80c186 microcontroller pins. it is implemented by connecting the tmrout1 output to an additional internal interrupt to create the watchdog timer interrupt. this interrupt is assigned to interrupt type 11h. the control register format is shown in figure 7-8. the systems programmer should program the timer (see section 8.2.2 on page 8-3) and then program the interrupt pin. figure 7-8 watchdog timer interrupt control register (wdcon, offset 42h) the value of wdcon at reset is 000fh. bits 15C5: reserved set to 0. bit 4: reserved must be set to 0 to ensure proper operation of the am186em and am188em microcontrollers. bit 3: mask (msk) this bit determines whether the watchdog timer can cause an interrupt. a 1 in this bit masks this interrupt source, preventing the watchdog timer from causing an interrupt. a 0 in this bit enables watchdog timer interrupts. this bit is duplicated in the interrupt mask register. see the interrupt mask register in section 7.3.11 on page 7-24. bits 2C0: priority (pr) this field determines the priority of the watchdog timer relative to the other interrupt signals, as shown in table 7-3 on page 7-14. 15 70 reserved msk pr2 pr1 pr0
interrupt control unit 7-19 7.3.6 serial port interrupt control register (spicon, offset 44h) (master mode) the serial port interrupt control register controls the operation of the asynchronous serial port interrupt source (spi, bit 10 in the interrupt request register). this interrupt is assigned to interrupt type 14h. the control register format is shown in figure 7-9. figure 7-9 serial port interrupt control register (spicon, offset 44h) the value of spicon at reset is 001fh. bits 15C5: reserved set to 0. bit 4: reserved set to 1. bit 3: mask (msk) this bit determines whether the serial port can cause an interrupt. a 1 in this bit masks this interrupt source, preventing the serial port from causing an interrupt. a 0 in this bit enables serial port interrupts. this bit is duplicated in the interrupt mask register. see the interrupt mask register in section 7.3.11 on page 7-24. bits 2C0: priority (pr2Cpr0) this field determines the priority of the serial port relative to the other interrupt signals. after a reset, the priority is 7. see table 7-3 on page 7-14. 15 70 msk res reserved 1 pr2 pr1 pr0
interrupt control unit 7-20 7.3.7 interrupt status register (intsts, offset 30h) (master mode) the interrupt status (intsts) register indicates the interrupt request status of the three timers. figure 7-10 interrupt status register (intsts, offset 30h) bit 15: dma halt (dhlt) when set to 1, halts any dma activity. this pin is automatically set to 1 when non-maskable interrupts occur and is reset when an iret instruction is executed. time-critical software, such as interrupt handlers, can modify this bit directly to inhibit dma transfers. because of the function of this register as an interrupt request register for the timers, the dhlt bit should not be modified by software when timer interrupts are enabled. bits 14C3: reserved bits 2C0: timer interrupt request (tmr2Ctmr0) when set to 1, these bits indicate that the corresponding timer has an interrupt request pending. (note that the timer tmr bit in the reqst register is the or of these timer interrupt requests.) 15 70 reserved tmr2 tmr1 tmr0 dhlt
interrupt control unit 7-21 7.3.8 interrupt request register (reqst, offset 2eh) (master mode) the hardware interrupt sources have interrupt request bits inside the interrupt controller. a read from this register yields the status of these bits. the interrupt request register is a read-only register. the format of the reqst register is shown in figure 7-11. the am186em and am188em microcontrollers define three new bits to report the state of int4, the watchdog timer, and the asynchronous serial port. for internal interrupts (spi, wd, d1, d0, and tmr), the corresponding bit is set to 1 when the device requests an interrupt. the bit is reset during the internally generated interrupt acknowledge. for int4Cint0 external interrupts, the corresponding bit (i4Ci0) reflects the current value of the external signal. the device must hold this signal high until the interrupt is serviced. generally the interrupt service routine signals the external device to remove the interrupt request. figure 7-11 interrupt request register (reqst, offset 2eh) the reqst register is undefined on reset. bits 15C11: reserved bit 10: serial port interrupt request (spi) this bit indicates the interrupt state of the serial port. if enabled, the spi bit is the logical or of all possible serial port interrupt sources (thre, rdr, brki, fer, per, and oer status bits). bit 9: watchdog timer interrupt request (wd) when this bit is set to 1, the watchdog timer has an interrupt pending. bits 8C4: interrupt requests (i4Ci0) when set to 1, the corresponding int pin has an interrupt pending (i.e., when int0 is pending, i0 is set). these bits reflect the status of the external pin. bits 3C2: dma channel interrupt request (d1Cd0) when set to 1, the corresponding dma channel has an interrupt pending. bit 1: reserved bit 0: timer interrupt request (tmr) this bit indicates the state of the timer interrupts. this bit is the logical or of the timer interrupt requests. when set to a 1, this bit indicates that the timer control unit has an interrupt pending. the interrupt status register indicates the specific timer that is requesting an interrupt. see section 7.3.7. 15 70 reserved res tmr d0 d1 i0 i1 i2 i3 i4 wd spi
interrupt control unit 7-22 7.3.9 in-service register (inserv, offset 2ch) (master mode) the am186em and am188em microcontrollers define three new bits to report the in-service state of int4, the virtual watchdog timer, and the asynchronous serial port. the format of the modified in-service register is shown in figure 7-12. the bits in the inserv register are set by the interrupt controller when the interrupt is taken. each bit in the register is cleared by writing the corresponding interrupt type to the end-of-interrupt (eoi) register. see table 7-1 on page 7-3. when an in-service bit is set, the microcontroller will not generate an interrupt request for the associated source, preventing an interrupt from interrupting itself if interrupts are enabled in the isr. special fully nested mode allows the int1Cint0 requests to circumvent this restriction for the int0 and int1 sources. figure 7-12 in-service register (inserv, offset 2ch) the inserv register is set to 0000h on reset. bits 15C11: reserved bit 10: serial port interrupt in-service (spi) this bit indicates the in-service state of the asynchronous serial port. bit 9: watchdog timer interrupt in-service (wd) this bit indicates the in-service state of the watchdog timer. bits 8C4: interrupt in-service (i4Ci0) these bits indicate the in-service state of the corresponding int pin. bits 3C2: dma channel interrupt in-service (d1Cd0) these bits indicate the in-service state of the corresponding dma channel. bit 1: reserved bit 0: timer interrupt in-service (tmr) this bit indicates the state of the in-service timer interrupts. this bit is the logical or of all the timer interrupt status bits. when set to a 1, this bit indicates that the corresponding timer interrupt status bit is in-service. 15 70 reserved res tmr d0 d1 i0 i1 i2 i3 i4 wd spi
interrupt control unit 7-23 7.3.10 priority mask register (primsk, offset 2ah) (master mode) the priority mask (primsk) register provides the value that determines the minimum priority level at which maskable interrupts can generate an interrupt. figure 7-13 priority mask register (primsk, offset 2ah) the value of primsk at reset is 0007h. bits 15C3: reserved set to 0. bits 2C0: priority field mask (prm2Cprm0) this field determines the minimum priority that is required in order for a maskable interrupt source to generate an interrupt. maskable interrupts with programmable priority values that are numerically higher than this field are masked. the possible values are zero (000b) to seven (111b). a value of seven (111b) allows all interrupt sources that are not masked to generate interrupts. a value of five (101b) allows only unmasked interrupt sources with a programmable priority of zero to five (000b to 101b) to generate interrupts. table 7-4 priority level priority pr2Cpr0 (high) 0 0 0 0b 1 0 0 1b 2 0 1 0b 3 0 1 1b 4 1 0 0b 5 1 0 1b 6 1 1 0b (low) 7 1 1 1b 15 70 000 000 00 0 0 0 0 prm2 prm1 prm0 0
interrupt control unit 7-24 7.3.11 interrupt mask register (imask, offset 28h) (master mode) the am186em and am188em microcontrollers define three new bits to report the mask state of the int4 control, watchdog timer interrupt control, and serial port interrupt control registers. the interrupt mask (imask) register is a read/write register. programming a bit in the imask register has the effect of programming the msk bit in the associated control register. the format of the imask register is shown in figure 7-14. do not write to the interrupt mask register while interrupts are enabled. to modify mask bits while interrupts are enabled, use the individual interrupt control registers. figure 7-14 interrupt mask register (imask, offset 28h) the imask register is set to 07fdh on reset. bits 15C11: reserved bit 10: serial port interrupt mask (spi) when set to 1, this bit indicates that the asynchronous serial port interrupt is masked. bit 9: virtual watchdog timer interrupt mask (wd) when set to 1, this bit indicates that the watchdog timer interrupt is masked. bits 8C4: interrupt mask (i4Ci0) when set to 1, an i4Ci0 bit indicates that the corresponding interrupt is masked. b its 3C2: dma channel interrupt masks (d1Cd0) when set to 1, a d1Cd0 bit indicates that the corresponding dma channel interrupt is masked. bit 1: reserved bit 0: timer interrupt mask (tmr) when set to 1, this bit indicates that interrupt requests from the timer control unit are masked. 15 70 reserved res tmr d0 d1 i0 i1 i2 i3 i4 wd spi
interrupt control unit 7-25 7.3.12 poll status register (pollst, offset 26h) (master mode) the poll status (pollst) register mirrors the current state of the poll register. the pollst register can be read without affecting the current interrupt request. but when the poll register is read, the current interrupt is acknowledged and the next interrupt takes its place in the poll register. figure 7-15 poll status register (pollst, offset 26h) bit 15: interrupt request (ireq) set to 1 if an interrupt is pending. when this bit is set to 1, the s4Cs0 field contains valid data. bits 14C5: reserved set to 0. bits 4C0: poll status (s4Cs0) indicates the interrupt type of the highest priority pending interrupt. 15 70 s4Cs0 ireq reserved
interrupt control unit 7-26 7.3.13 poll register (poll, offset 24h) (master mode) when the poll register is read, the current interrupt is acknowledged and the next interrupt takes its place in the poll register. the poll status register mirrors the current state of the poll register, but the poll status register can be read without affecting the current interrupt request. figure 7-16 poll register (poll, offset 24h) bit 15: interrupt request (ireq) set to 1 if an interrupt is pending. when this bit is set to 1, the s4Cs0 field contains valid data. bits 14C5: reserved set to 0. bits 4C0: poll status (s4Cs0) indicates the interrupt type of the highest priority pending interrupt. reading the poll register acknowledges the highest priority pending interrupt and enables the next interrupt to advance into the register. although the is bit is set, the interrupt service routine does not begin execution automatically. the application software must execute the appropriate isr. 15 70 s4Cs0 ireq reserved
interrupt control unit 7-27 7.3.14 end-of-interrupt register (eoi, offset 22h) (master mode) the end-of-interrupt (eoi) register is a write-only register. the in-service flags in the in- service register (see section 7.3.9 on page 7-22) are reset by writing to the eoi register. before executing the iret instruction that ends an interrupt service routine (isr), the isr should write to the eoi register to reset the is bit for the interrupt. the specific eoi reset is the most secure method to use for resetting is bits. figure 7-17 shows example code for a specific eoi reset. see table 7-1 on page 7-3 for specific eoi values. figure 7-17 example eoi assembly code figure 7-18 end-of-interrupt register (eoi, offset 22h) bit 15: non-specific eoi (nspec) the nspec bit determines the type of eoi command. when written as a 1, nspec indicates non-specific eoi. when written as a 0, nspec indicates the specific eoi interrupt type in s4Cs0. bits 14C5: reserved bits 4C0: source eoi type (s4Cs0) specifies the eoi type of the interrupt that is currently being processed. see table 7-1 on page 7-3. ... ... ;isr code ... mov dx, eoi_addr exit: mov ax,int_type ;load the interrupt type in ax out dx,ax ;write the interrupt type to eoi popa iret ;return from interrupt 15 70 s4Cs0 nspec reserved
interrupt control unit 7-28 7.4 slave mode operation when slave mode is used, the microcontrollers internal interrupt controller is used as a slave controller to an external master interrupt controller. the internal interrupts are monitored by the internal interrupt controller, while the external controller functions as the system master interrupt controller. on reset, the microcontroller is in master mode. to activate slave mode operation, bit 14 of the relocation register must be set (see figure 4-2 on page 4-4). because of pin limitations caused by the need to interface to an external 82c59a master, the internal interrupt controller does not accept external inputs. however, there are enough interrupt controller inputs (internally) to dedicate one to each timer. in slave mode, each timer interrupt source has its own mask bit, is bit, and control word. the int4, watchdog timer, and serial port interrupts are not available in slave mode. in slave mode, each peripheral must be assigned a unique priority to ensure proper interrupt controller operation. the programmer must assign correct priorities and initialize interrupt control registers before enabling interrupts. 7.4.1 slave mode interrupt nesting slave mode operation allows nesting of interrupt requests. when an interrupt is acknowledged, the priority logic masks off all priority levels except those with equal or higher priority. 7.4.2 slave mode interrupt controller registers the interrupt controller registers for slave mode are shown in table 7-5. all registers can be read and written, unless specified otherwise. table 7-5 interrupt controller registers in slave mode offset register mnemonic register name affected pins comments 3ah t2intcon timer 2 interrupt control interrupt type xxxxx101 38h t1intcon timer 1 interrupt control tmrin1 tmrout1 interrupt type xxxxx100 36h dma1con dma 1 interrupt control interrupt type xxxxx011 34h dma0con dma 0 interrupt control interrupt type xxxxx010 32h t0intcon timer 0 interrupt control tmrin0 tmrout0 interrupt type xxxxx000 30h intsts interrupt status 2eh reqst interrupt request read only 2ch inserv in-service read only 2ah primsk priority mask 28h imask interrupt mask 22h eoi specific eoi write only 20h intvec interrupt vector
interrupt control unit 7-29 7.4.3 timer and dma interrupt control registers (t0intcon, offset 32h, t1intcon, offset 38h, t2intcon, offset 3ah, dma0con, offset 34h, dma1con, offset 36h) (slave mode) in slave mode, there are three separate registers for the three timers. in master mode, all three timers are masked and prioritized in one register, tcucon. in slave mode, the two dma control registers retain their functionality and addressing from master mode. figure 7-19 timer and dma interrupt control registers (t0intcon, t1intcon, t2intcon, dma0con, dma1con, offsets 32h, 38h, 3ah, 34h, and 36h) these registers are set to 000fh on reset. bits 15C4: reserved set to 0. bit 3: mask (msk) this bit determines whether the interrupt source can cause an interrupt. a 1 in this bit masks the interrupt source, preventing the source from causing an interrupt. a 0 in this bit enables interrupts from the source. this bit is duplicated in the interrupt mask register. see the interrupt mask register in section 7.4.8 on page 7-34. bits 2C0: priority level (pr2Cpr0) this field determines the priority of the interrupt source relative to the other interrupt signals, as shown in table 7-3 on page 7-14. 15 70 pr2 pr1 pr0 msk reserved
interrupt control unit 7-30 7.4.4 interrupt status register (intsts, offset 30h) (slave mode) the interrupt status register controls dma activity when non-maskable interrupts occur and indicates the current interrupt status of the three timers. figure 7-20 interrupt status register (intsts, offset 30h) the intsts register is set to 0000h on reset. bit 15: dma halt (dhlt) when set to 1, halts any dma activity. automatically set to 1 when non-maskable interrupts occur and reset when an iret instruction is executed. bits 14C3: reserved bits 2C0: timer interrupt request (tmr2Ctmr0) when set to 1, indicates the corresponding timer has an interrupt request pending. 15 70 reserved tmr2 tmr1 tmr0 dhlt
interrupt control unit 7-31 7.4.5 interrupt request register (reqst, offset 2eh) (slave mode) the internal interrupt sources have interrupt request bits inside the interrupt controller. a read from this register yields the status of these bits. the interrupt request register is a read-only register. the format of the interrupt request register is shown in figure 7-21. for internal interrupts (d1, d0, tmr2, tmr1, and tmr0), the corresponding bit is set to 1 when the device requests an interrupt. the bit is reset during the internally generated interrupt acknowledge. figure 7-21 interrupt request register (reqst, offset 2eh) the reqst register is set to 0000h on reset. bits 15C6: reserved bits 5C4: timer 2/timer 1 interrupt request (tmr2Ctmr1) when set to 1, these bits indicate the state of any interrupt requests from the associated timer. b its 3C2: dma channel interrupt request (d1Cd0) when set to 1, d1Cd0 indicate that the corresponding dma channel has an interrupt pending. bit 1: reserved bit 0: timer 0 interrupt request (tmr0) when set to 1, this bit indicates the state of an interrupt request from timer 0. 15 70 reserved d0 d1 tmr1 tmr2 res tmr0
interrupt control unit 7-32 7.4.6 in-service register (inserv, offset 2ch) (slave mode) the format of the in-service register is shown in figure 7-22. the bits in the in-service register are set by the interrupt controller when the interrupt is taken. the in-service bits are cleared by writing to the end-of-interrupt (eoi) register. figure 7-22 in-service register (inserv, offset 2ch) the inserv register is set to 0000h on reset. bits 15C6: reserved bits 5C4: timer 2/timer 1 interrupt in-service (tmr2Ctmr1) when set to 1, these bits indicate that the corresponding timer interrupt is currently being serviced. bits 3C2: dma channel interrupt in-service (d1Cd0) when set to 1, the corresponding dma channel is currently being serviced. bit 1: reserved bit 0: timer 0 interrupt in-service (tmr0) when set to 1, this bit indicates timer 0 is currently being serviced. 15 70 reserved d0 d1 tmr1 tmr2 res tmr0
interrupt control unit 7-33 7.4.7 priority mask register (primsk, offset 2ah) (slave mode) the format of the priority mask register is shown in figure 7-23. the priority mask register provides the value that determines the minimum priority level at which maskable interrupts can generate an interrupt. figure 7-23 priority mask register (primsk, offset 2ah) the value of the primsk register at reset is 0007h. bits 15C3: reserved bits 2C0: priority field mask (prm2Cprm0) this field determines the minimum priority which is required in order for a maskable interrupt source to generate an interrupt. a value of seven (111b) allows all interrupt sources that are not masked to generate interrupts. a value of five (101b) allows only unmasked interrupt sources with a programmable priority of zero to five (000b to 101b) to generate interrupts. table 7-6 priority level priority pr2Cpr0 (high) 0 0 0 0b 1 0 0 1b 2 0 1 0b 3 0 1 1b 4 1 0 0b 5 1 0 1b 6 1 1 0b (low) 7 1 1 1b 15 70 prm0 prm2 prm1 reserved
interrupt control unit 7-34 7.4.8 interrupt mask register (imask, offset 28h) (slave mode) the format of the interrupt mask register is shown in figure 7-24. the interrupt mask register is a read/write register. programming a bit in the interrupt mask register has the effect of programming the msk bit in the associated control register. figure 7-24 interrupt mask register (imask, offset 28h) the imask register is set to 003dh on reset. bits 15C6: reserved bits 5C4: timer 2/timer 1 interrupt mask (tmr2Ctmr1) these bits indicate the state of the mask bit of the timer interrupt control register and when set to a 1, indicate which source has its interrupt requests masked. bits 3C2: dma channel interrupt mask (d1Cd0) these bits indicate the state of the mask bits of the corresponding dma control register. bit 1: reserved bit 0: timer 0 interrupt mask (tmr0) this bit indicates the state of the mask bit of the timer interrupt control register and when set to a 1, indicates timer 0 has its interrupt request masked. 15 70 reserved d0 d1 tmr1 tmr2 res tmr0
interrupt control unit 7-35 7.4.9 specific end-of-interrupt register (eoi, offset 22h) (slave mode) in slave mode, a write to the eoi register resets an in-service bit of a specific priority. the user supplies a three-bit priority-level value that points to an in-service bit to be reset. the command is executed by writing the correct value in the specific eoi register at offset 22h. figure 7-25 specific end-of-interrupt register (eoi, offset 22h) the eoi register is undefined on reset. bits 15C3: reserved write as 0. bits 2C0: interrupt type (l2Cl0) encoded value indicating the priority of the is (interrupt service) bit to be reset. writes to these bits cause an eoi to be issued for the interrupt type in slave mode. write-only register. 15 70 000 000 00 00 l2Cl0 000
interrupt control unit 7-36 7.4.10 interrupt vector register (intvec, offset 20h) (slave mode) vector generation in slave mode is exactly like that of an 8259a or 82c59a slave. the interrupt controller generates an 8-bit interrupt type that the cpu shifts left two bits (multiplies by four) to generate an offset into the interrupt vector table. figure 7-26 interrupt vector register (intvec, offset 20h) the intvec register is undefined on reset. bits 15C8: reserved read as 0. bits 7C3: interrupt type (t4Ct0) sets the five most significant bits of the interrupt types for the internal interrupt type. the interrupt controller itself provides the lower three bits of the interrupt type, as determined by the priority level of the interrupt request. see table 7- 5 on page 7-15. bits 2C0: reserved read as 0. 15 70 000 000 00 0 0 0 t4Ct0
timer control unit 8-1 chapter 8 timer control unit 8.1 overview there are three 16-bit programmable timers in the am186em and am188em microcontrollers. timers 0 and 1 are highly versatile and are each connected to two external pins (each one has an input and an output). these two timers can be used to count or time external events, or they can be used to generate nonrepetitive or variable-duty-cycle waveforms. timer 1 can also be configured as a watchdog timer. the watchdog timer provides a mechanism for detecting software crashes or hangs. the tmrout1 output is internally connected to the watchdog timer interrupt. software developers must first program the timer1 mode/control, count, and max count registers, and then program the watchdog timer interrupt control register (see figure 7-8 on page 7-18). the timer1 count register must be reloaded at intervals less than the timer1 max count to assure the watchdog interrupt is not taken. if the code crashes or hangs, the timer1 countdown can cause a watchdog interrupt. timer 2 is not connected to any external pins. it can be used for real-time coding and time- delay applications. it can also be used as a prescale to timer 0 and timer 1 or as a dma request source. 8.2 programmable registers the timers are controlled by eleven 16-bit registers (see table 8-1) that are located in the peripheral control block. table 8-1 timer control unit register summary the timer-count registers contain the current value of a timer. the timer-count registers can be read or written at any time, regardless of whether the corresponding timer is running. the microcontroller increments the value of a timer-count register each time a timer event occurs. offset from pcb register mnemonic register name 56h t0con timer 0 mode/control 5eh t1con timer 1 mode/control 66h t2con timer 2 mode/control 50h t0cnt timer 0 count 58h t1cnt timer 1 count 60h t2cnt timer 2 count 52h t0cmpa timer 0 maxcount compare a 54h t0cmpb timer 0 maxcount compare b 5ah t1cmpa timer 1 maxcount compare a 5ch t0cmpb timer 1 maxcount compare b 62h t2cmpa timer 2 maxcount compare a
timer control unit 8-2 each timer also has a corresponding maximum-count register that defines the maximum value for the timer. when the timer reaches the maximum value, it resets to 0 during the same clock cycle. (the value in the timer-count register never equals the maximum-count register.) in addition, timers 0 and 1 have a secondary maximum-count register. using both the primary and secondary maximum-count registers lets the timer alternate between two maximum values. if the timer is programmed to use only the primary maximum-count register, the timer output pin switches low for one clock cycle, the clock cycle after the maximum value is reached. if the timer is programmed to use both of its maximum-count registers, the output pin creates a waveform by indicating which maximum-count register is currently in control. the duty cycle and frequency of the waveform depend on the values in the alternating maximum- count registers. 8.2.1 timer operating frequency each timer is serviced on every fourth clock cycle. therefore, a timer can operate at a maximum speed of one-quarter of the internal clock frequency. a timer can be clocked externally at the same maximum frequency of one-fourth of the internal clock frequency. however, because of internal synchronization and pipelining of the timer circuitry, the timer output takes up to six clock cycles to respond to the clock or gate input. the timers are run by the processors internal clock. if power-save mode is in effect, the timers operate at the reduced power-save clock rate.
timer control unit 8-3 8.2.2 timer 0 and timer 1 mode and control registers (t0con, offset 56h, t1con, offset 5eh) these registers control the functionality of timer 0 and timer 1. see figure 8-1. figure 8-1 timer 0 and timer 1 mode and control registers (t0con, t1con, offsets 56h and 5eh) the value of t0con and t1con at reset is 0000h. bit 15: enable bit (en) when set to 1, the timer is enabled. when set to 0, the timer is inhibited from counting. this bit can only be written with the inh bit set at the same time. bit 14: inhibit bit (inh ) allows selective updating of enable (en) bit. when set to 1 during a write, en can also be modified. when set to 0 during a write, writes to en are ignored. this bit is not stored and is always read as 0. bit 13: interrupt bit (int) when set to 1, an interrupt request is generated when the count register equals a maximum count. if the timer is configured in dual maxcount mode, an interrupt is generated each time the count reaches maxcount a or maxcount b. when int is set to 0, the timer will not issue interrupt requests. if the enable bit is cleared after an interrupt request has been generated but before the pending interrupt is serviced, the interrupt request will still be present. bit 12: register in use bit (riu) when the maxcount compare a register is being used for comparison to the timer count value, this bit is set to 0. when the maxcount compare b register is being used, this bit is set to 1. bits 11C6: reserved set to 0. bit 5: maximum count bit (mc) the mc bit is set to 1 when the timer reaches a maximum count. in dual maxcount mode, the bit is set each time either maxcount compare a or b register is reached. this bit is set regardless of the timer interrupt-enable bit. the mc bit can be used to monitor timer status through software polling instead of through interrupts. bit 4: retrigger bit (rtg) determines the control function provided by the timer input pin. when set to 1, a 0 to 1 edge transition on tmrin0 or tmrin1 resets the count. when set to 0, a high input enables counting and a low input holds the timer value. this bit is ignored when external clocking (ext=1) is selected. bit 3: prescaler bit (p) when set to 1, the timer is prescaled by timer 2. when set to 0, the timer counts up every fourth clkout period. this bit is ignored when external clocking is enabled (ext=1). 15 70 en int inh riu 0 p ext mc rtg alt cont 00000
timer control unit 8-4 bit 2: external clock bit (ext) when set to 1, an external clock is used. when set to 0, the internal clock is used. bit 1: alternate compare bit (alt) when set to 1, the timer counts to maxcount compare a, then resets the count register to 0. then the timer counts to maxcount compare b, resets the count register to zero, and starts over with maxcount compare a. if alt is clear, the timer counts to maxcount compare a and then resets the count register to zero and starts counting again against maxcount compare a. in this case, maxcount compare b is not used. bit 0: continuous mode bit (cont) when set to 1, cont causes the associated timer to run in the normal continuous mode. when cont is set to 0, en is cleared after each timer count sequence and the timer clears and then halts on reaching the maximum count. if cont=0 and alt=1, the timer counts to the maxcount compare a register value and resets, then it counts to the b register value and resets and halts.
timer control unit 8-5 8.2.3 timer 2 mode and control register (t2con, offset 66h) this register controls the functionality of timer 2. see figure 8-2. figure 8-2 timer 2 mode and control register (t2con, offset 66h) the value of t2con at reset is 0000h. bit 15: enable bit (en) when en is set to 1, the timer is enabled. when set to 0, the timer is inhibited from counting. do not write to this bit unless the inh bit is set to 1 during the same write. bit 14: inhibit bit (inh ) allows selective updating of enable (en) bit. when inh is set to 1 during a write, en can be modified on the same write. when inh is set to 0 during a write, writes to en are ignored. this bit is not stored and is always read as 0. bit 13: interrupt bit (int) when int is set to 1, an interrupt request is generated when the count register equals a maximum count. when int is set to 0, the timer will not issue interrupt requests. if the en enable bit is cleared after an interrupt request has been generated, but before the pending interrupt is serviced, the interrupt request remains active. bits 12C6: reserved set to 0. bit 5: maximum count bit (mc) the mc bit is set to 1 when the timer reaches its maximum count. this bit is set regardless of the timer interrupt-enable bit. the mc bit can be used to monitor timer status through software polling instead of through interrupts. bits 4C1: reserved set to 0. bit 0: continuous mode bit (cont) when cont is set to 1, it causes the associated timer to run continuously. when set to 0, en is cleared after each timer count sequence and the timer halts on reaching the maximum count. 15 70 en int inh 0 mc cont 00000 000 0 0
timer control unit 8-6 8.2.4 timer count registers (t0cnt, offset 50h, t1cnt, offset 58h, t2cnt, offset 60h) these registers can be incremented by one every four internal processor clocks. timer 0 and timer 1 can also be configured to increment based on the tmrin0 and tmrin1 external signals, or they can be prescaled by timer 2. see figure 8-3. the count registers are compared to maximum count registers and various actions are triggered based on reaching a maximum count. figure 8-3 timer count registers (t0cnt, t1cnt, t2cnt, offsets 50h, 58h, and 60h) the value of these registers at reset is undefined. bits 15C0: timer count value (tc15Ctc0) this register contains the current count of the associated timer. the count is incremented every fourth processor clock in internal clocked mode, or each time the timer 2 maxcount is reached if prescaled by timer 2. timer 0 and timer 1 can be configured for external clocking based on the tmrin0 and tmrin1 signals. 15 70 tc15Ctc0
timer control unit 8-7 8.2.5 timer maxcount compare registers (t0cmpa, offset 52h, t0cmpb, offset 54h, t1cmpa, offset 5ah, t1cmpb, offset 5ch, t2cmpa, offset 62h) these registers serve as comparators for their associated count registers. timer 0 and timer 1 each have two maximum count compare registers. see figure 8-4. timer 0 and timer 1 can be configured to count and compare to register a and then count and compare to register b. using this method, the tmrout0 or tmrout1 signals can be used to generate waveforms of various duty cycles. timer 2 has one compare register, t2cmpa. if a maximum count compare register is set to 0000h, the timer associated with that compare register will count from 0000h to ffffh before requesting an interrupt. with a 40-mhz clock, a timer configured this way interrupts every 6.5536 ms. figure 8-4 timer maxcount compare registers (t0cmpa, t0cmpb, t1cmpa, t1cmpb, t2cmpa, offsets 52h, 54h, 5ah, 5ch, and 62h) the value of these registers at reset is undefined. bits 15C0: timer compare value (tc15Ctc0) this register contains the maximum value a timer will count to before resetting its count register to 0. 15 70 tc15Ctc0
timer control unit 8-8
dma controller 9-1 chapter 9 dma controller 9.1 overview direct memory access (dma) permits transfer of data between memory and peripherals without cpu involvement. the dma unit in the am186em and am188em microcontrollers provides two high-speed dma channels. data transfers can occur between memory and i/o spaces (e.g., memory to i/o) or within the same space (e.g., memory-to-memory or i/o-to-i/o). either bytes or words can be transferred to or from even or odd addresses on the am186em. (the am188em microcontroller does not support word transfers.) two bus cycles (a minimum of eight clocks) are necessary for each data transfer. each channel accepts a dma request from one of two sources: the channel request pin (drq1Cdrq0) or timer 2. the two dma channels can be programmed with different priorities to resolve simultaneous dma requests, and transfers on one channel can interrupt the other channel. 9.2 dma operation the format of the dma control block is shown in table 9-1. six registers in the peripheral control block define the operation of each channel. the dma registers consist of a 20-bit source address (2 registers), a 20-bit destination address (2 registers), a 16-bit transfer count register, and a 16-bit control register. table 9-1 dma controller register summary the dma transfer count register (dtc) specifies the number of dma transfers to be performed. up to 64 kbytes or 64 kwords can be transferred with automatic termination. the dma control registers define the channel operations (see figure 9-1). all registers can be modified or altered during any dma activity. any changes made to these registers are reflected immediately in dma operation. offset from pcb register mnemonic register name cah d0con dma 0 control dah d1con dma 1 control c8h d0tc dma 0 transfer count d8h d1tc dma 1 transfer count c6h d0dsth dma 0 destination address high d6h d1dsth dma 1 destination address high c4h d0dstl dma 0 destination address low d4h d1dstl dma 1 destination address low c2h d0srch dma 0 source address high d2h d1srch dma 1 source address high c0h d0srcl dma 0 source address low d0h d1srcl dma 1 source address low
dma controller 9-2 figure 9-1 dma unit block diagram 9.3 programmable dma registers the sections on the following pages describe the control registers that are used to configure and operate the two dma channels. source address ch. 1 source address ch. 0 20-bit adder/subtractor dma control logic request selection logic adder control logic 20 20 channel control register 1 channel control register 0 16 drq1 drq0 internal address/data bus timer request interrupt request transfer counter ch. 1 destination address ch. 1 destination address ch. 0 transfer counter ch. 0
dma controller 9-3 9.3.1 dma control registers (d0con, offset cah, d1con, offset dah) the dma control registers (see figure 9-2) determine the mode of operation for the dma channels. these registers specify the following options: n whether the destination address is memory or i/o space n whether the destination address is incremented, decremented, or maintained constant after each transfer n whether the source address is memory or i/o space n whether the source address is incremented, decremented, or maintained constant after each transfer n if dma activity ceases after a programmed number of dma cycles n if an interrupt is generated after the last transfer n the mode of synchronization n the relative priority of one dma channel with respect to the other dma channel n whether timer 2 dma requests are enabled or disabled n whether bytes or words are transferred the dma channel control registers can be changed while the channel is operating. any changes made during dma operations affect the current dma transfer. figure 9-2 dma control registers (d0con, d1con, offsets cah and dah) the value of d0con and d1con at reset is fff9h. bit 15: destination address space select (dm/io ) selects memory or i/o space for the destination address. when dm/io is set to 1, the destination address is in memory space. when set to 0, the destination address is in i/o space. bit 14: destination decrement (ddec) when ddec is set to 1, the destination address is automatically decremented after each transfer. the address decrements by 1 or 2, depending on the byte/word bit ( b /w, bit 0). the address remains constant if the increment and decrement bits are set to the same value (00b or 11b). bit 13: destination increment (dinc) when dinc is set to 1, the destination address is automatically incremented after each transfer. the address increments by 1 or 2, depending on the byte/word bit ( b /w, bit 0). the address remains constant if the increment and decrement bits are set to the same value (00b or 11b). bit 12: source address space select (sm/io ) when sm/io is set to 1, the source address is in memory space. when set to 0, the source address is in i/o space. 15 70 dm/io dinc ddec sm/io sinc sdec b /w st chg res tc int syn p tdrq
dma controller 9-4 bit 11: source decrement (sdec) when sdec is set to 1, the source address is automatically decremented after each transfer. the address decrements by 1 or 2 depending on the byte/word bit (b /w, bit 0). the address remains constant if the increment and decrement bits are set to the same value (00b or 11b). bit 10: source increment (sinc) when sinc is set to 1, the source address is automatically incremented after each transfer. the address increments by 1 or 2 depending on the byte/word bit (b /w, bit 0). the address remains constant if the increment and decrement bits are set to the same value (00b or 11b). bit 9: terminal count (tc) the dma decrements the transfer count for each dma transfer. when tc is set to 1, source or destination synchronized dma transfers terminate when the count reaches 0. when tc is set to 0, source or destination synchronized dma transfers do not terminate when the count reaches 0. unsynchronized dma transfers always terminate when the count reaches 0, regardless of the setting of this bit. bit 8: interrupt (int) when int is set to 1, the dma channel generates an interrupt request on completion of the transfer count. the tc bit must also be set to generate an interrupt. bits 7C6: synchronization type (syn1Csyn0) the syn1Csyn0 bits select channel synchronization as shown in table 9-2. for more information on dma synchronization, see section 9.4 on page 9-10. table 9-2 synchronization type bit 5: relative priority (p) when p is set to 1, it selects high priority for this channel relative to the other channel during simultaneous transfers. bit 4: timer enable/disable request (tdrq) when tdrq is set to 1, it enables dma requests from timer 2. when set to 0, tdrq disables dma requests from timer 2. bit 3: reserved bit 2: change start bit (chg) this bit must be set to 1 during a write to allow modification of the st bit. when chg is set to 0 during a write, st is not altered when writing the control word. bit 1: start/stop dma channel (st) the dma channel is started when the start bit is set to 1. this bit can be modified only when the chg bit is set to a 1 during the same register write. bit 0: byte/word select (b /w) on the am186em microcontroller, when b /w is set to 1, word transfers are selected. when b /w is set to 0, byte transfers are selected. word transfers are not supported on the am188em microcontroller. syn1 syn0 sync type 0 0 unsynchronized 0 1 source synch 1 0 destination synch 1 1 reserved
dma controller 9-5 9.3.2 dma transfer count registers (d0tc, offset c8h, d1tc, offset d8h) each dma channel maintains a 16-bit dma transfer count register (dtc). this register is decremented after every dma cycle, regardless of the state of the tc bit in the dma control register. however, if the tc bit in the dma control word is set or if unsynchronized transfers are programmed, dma activity terminates when the transfer count register reaches 0. figure 9-3 dma transfer count registers (d0tc, d1tc, offsets c8h and d8h) the value of d0tc and d1tc at reset is undefined. bits 15C0: dma transfer count (tc15Ctc0) contains the transfer count for a dma channel. value is decremented by 1 after each transfer. 15 70 tc15Ctc0
dma controller 9-6 9.3.3 dma destination address high register (high order bits) (d0dsth, offset c6h, d1dsth, offset d6h) each dma channel maintains a 20-bit destination and a 20-bit source register. each register takes up two full 16-bit registers (the high register and the low register) in the peripheral control block. for each dma channel to be used, all four registers must be initialized. these registers can be individually incremented or decremented after each transfer. if word transfers are performed, the address is incremented or decremented by 2 after each transfer. if byte transfers are performed, the address is incremented or decremented by 1. each register can point into either memory or i/o space. the user must program the upper four bits to 0000b in order to address the normal 64k i/o space. since the dma channels can perform transfers to or from odd addresses, there is no restriction on values for the destination and source address registers. higher transfer rates can be achieved on the am186em microcontroller if all word transfers are performed to or from even addresses so that accesses occur in single, 16-bit bus cycles. figure 9-4 dma destination address high register (d0dsth, d1dsth, offsets c6h and d6h) the value of d0dsth and d1dsth at reset is undefined. bits 15C4: reserved bits 3C0: dma destination address high (dda19Cdda16) these bits are driven onto a19Ca16 during the write phase of a dma transfer. 15 70 reserved dda19Cdda16
dma controller 9-7 9.3.4 dma destination address low register (low order bits) (d0dstl, offset c4h, d1dstl, offset d4h) figure 9-5 shows the dma destination address low register. the sixteen bits of this register are combined with the four bits of the dma destination address high register (see figure 9-4) to produce a 20-bit destination address. figure 9-5 dma destination address low register (d0dstl, d1dstl, offsets c4h and d4h) the value of d0dstl and d1dstl at reset is undefined. bits 15C0: dma destination address low (dda15Cdda0) these bits are driven onto a15Ca0 during the write phase of a dma transfer. 15 70 dda15Cdda0
dma controller 9-8 9.3.5 dma source address high register (high order bits) (d0srch, offset c2h, d1srch, offset d2h) each dma channel maintains a 20-bit destination and a 20-bit source register. each register takes up two full 16-bit registers (the high register and the low register) in the peripheral control block. for each dma channel to be used, all four registers must be initialized. these registers can be individually incremented or decremented after each transfer. if word transfers are performed, the address is incremented or decremented by 2 after each transfer. if byte transfers are performed, the address is incremented or decremented by 1. each register can point into either memory or i/o space. the user must program the upper four bits to 0000b in order to address the normal 64k i/o space. since the dma channels can perform transfers to or from odd addresses, there is no restriction on values for the destination and source address registers. higher transfer rates can be achieved on the am186em microcontroller if all word transfers are performed to or from even addresses so that accesses occur in single, 16-bit bus cycles. figure 9-6 dma source address high register (d0srch, d1srch, offsets c2h and d2h) the value of d0srch and d1srch at reset is undefined. bits 15C4: reserved bits 3C0: dma source address high (dsa19Cdsa16) these bits are driven onto a19Ca16 during the read phase of a dma transfer. 15 70 reserved dsa19Cdsa16
dma controller 9-9 9.3.6 dma source address low register (low order bits) (d0srcl, offset c0h, d1srcl, offset d0h) figure 9-7 shows the dma source address low register. the sixteen bits of this register are combined with the four bits of the dma source address high register (see figure 9-6) to produce a 20-bit source address. figure 9-7 dma source address low register (d0srcl, d1srcl, offsets c0h and d0h) the value of d0srcl and d1srcl at reset is undefined. bits 15C0: dma source address low (dsa15Cdsa0) these bits are driven onto a15Ca0 during the read phase of a dma transfer. 15 70 dsa15Cdsa0
dma controller 9-10 9.4 dma requests data transfers can be either source or destination synchronizedeither the source of the data or the destination of the data can request the data transfer. dma transfers can also be unsynchronized (i.e., the transfer takes place continually until the correct number of transfers has occurred). during source synchronized or unsynchronized transfers, the dma channel can begin a transfer immediately after the end of the previous dma transfer, and a complete transfer can occur every two bus cycles or eight clock cycles (assuming no wait states). when destination synchronization is performed, data is not fetched from the source address until the destination device signals that it is ready to receive it. when destination synchronized transfers are requested, the dma controller relinquishes control of the bus after every transfer. if no other bus activity is initiated, another dma cycle begins after two processor clocks. this allows the destination device time to remove its request if another transfer is not desired. when the dma controller relinquishes the bus during destination synchronized transfers, the cpu can initiate a bus cycle. as a result, a complete bus cycle is often inserted between destination-synchronized transfers. table 9-3 shows the maximum dma transfer rates based on the different synchronization strategies. table 9-3 maximum dma transfer rates maximum dma transfer rate (mbytes/sec) synchronization type 40 mhz 33 mhz 25 mhz 20 mhz unsynchronized 10 8.25 6.25 5 source synch 10 8.25 6.25 5 destination synchronized (cpu needs bus) 6.6 5.5 4.16 3.3 destination synchronized (cpu does not need bus) 8 6.6 5 4
dma controller 9-11 9.4.1 synchronization timing drq1 or drq0 must be deasserted before the end of the dma transfer to prevent another dma cycle from occurring. the timing for the required deassertion depends on whether the transfer is source-synchronized or destination-synchronized. 9.4.1.1 source synchronization timing figure 9-8 shows a typical source-synchronized dma transfer. the drq signal must be deasserted at least four clocks before the end of the transfer (at t1 of the deposit phase). if more transfers are not required, a source-synchronized transfer allows the source device at least three clock cycles from the time it is acknowledged to deassert its drq line. figure 9-8 source-synchronized dma transfers notes: 1. this source-synchronized transfer is not followed immediately by another dma transfer. 2. this source-synchronized transfer is immediately followed by another dma transfer because drq is not deasserted soon enough. 9.4.1.2 destination synchronization timing figure 9-9 shows a typical destination-synchronized dma transfer. a destination- synchronized transfer differs from a source-synchronized transfer in that two idle states are added to the end of the deposit cycle. the two idle states allow the destination device to deassert its drq signal four clocks before the end of the cycle. without the two idle states, the destination device would not have time to deassert its drq signal. because of the two extra idle states, a destination-synchronized dma channel allows other bus masters to take the bus during the idle states. the cpu, the refresh control unit, and another dma channel can all access the bus during the idle states. t1 t2 t3 t4 t1 t2 t3 t4 clkout drq (first case) drq (second case) fetch cycle fetch cycle 1 2
dma controller 9-12 figure 9-9 destination synchronized dma transfers notes: 1. this destination-synchronized transfer is not followed immediately by another dma transfer. 2. this destination-synchronized transfer is immediately followed by another dma transfer because drq is not deasserted soon enough. 9.4.2 dma acknowledge no explicit dma acknowledge signal is provided. since both source and destination registers are maintained, a read from a requesting source or a write to a requesting destination should be used as the dma acknowledge signal. since the chip-select lines can be programmed to be active for a given block of memory or i/o space, and the dma source and destination address registers can be programmed to point to the same given block, a chip-select line could be used to indicate a dma acknowledge. 9.4.3 dma priority the dma channels can be programmed so that one channel is always given priority over the other, or they can be programmed to alternate cycles when both have dma requests pending (see section 9.3.1, bit 5, the p bit). dma cycles always have priority over internal cpu cycles except between internally locked memory accesses or word accesses to odd memory locations. however, an external bus hold takes priority over an internal dma cycle. because an interrupt request cannot suspend a dma operation and the cpu cannot access memory during a dma cycle, interrupt latency time suffers during sequences of continuous dma cycles. an nmi request, however, causes all internal dma activity to halt. this allows the cpu to respond quickly to the nmi request. 9.4.4 dma programming dma cycles occur whenever the st bit of the control register is set. if synchronized transfers are programmed, a drq must also be generated. therefore, the source and destination transfer address registers and the transfer count register (if used) must be programmed before the st bit is set. t1 t2 t3 t4 t1 t2 t3 t4 clkout drq (first case) drq (second case) fetch cycle deposit cycle 1 2 ti ti
dma controller 9-13 each dma register can be modified while the channel is operating. if the chg bit is set to 0 when the control register is written, the st bit of the control register will not be modified by the write. if multiple channel registers are modified, an internally locked string transfer should be used to prevent a dma transfer from occurring between updates to the channel registers. 9.4.5 dma channels on reset on reset, the state of the dma channels is as follows: n the st bit for each channel is reset. n any transfer in progress is aborted. n the values of the transfer count registers, source address registers, and destination address registers are undefined.
dma controller 9-14
asynchronous serial port 10-1 chapter 10 asynchronous serial port 10.1 overview the am186em and am188em microcontrollers provide an asynchronous serial port. the asynchronous serial port is a two-pin interface that permits full-duplex bidirectional data transfer. the asynchronous serial port supports the following features: n full-duplex operation n 7-bit or 8-bit data transfers n odd parity, even parity, or no parity n 1 or 2 stop bits if additional rs-232 signals are required, they can be created with available pio pins (see section 12.1 on page 12-1). the asynchronous serial port transmit and receive sections are double-buffered. break character recognition, framing, parity, and overrun error detection are provided. exception interrupt generation is programmed by the user. the transmit/receive clock is based on the internal processor clock internally divided down to the serial port operating frequency. if power-save mode is in effect, the divide factor must be reprogrammed. the serial port permits 7-bit and 8-bit data transfers. dma transfers through the serial port are not supported. the serial port generates one interrupt for all serial port events (transmit complete, data received, or error). the serial port status register contains the reason for the serial port interrupt. the interrupt type assigned to the serial port is 14h. the serial port can be used in power-save mode, but the transfer rate must be adjusted to correctly reflect the new internal operating frequency and the serial port must not receive any information until the frequency is changed. 10.2 programmable registers the asynchronous serial port is programmed through the use of five, 16-bit peripheral registers. see table 10-1. table 10-1 asynchronous serial port register summary offset from pcb register mnemonic register name 80h spct serial port control 82h spsts serial port status 84h sptd serial port transmit data 86h sprd serial port receive data 88h spbaud serial port baud rate divisor
asynchronous serial port 10-2 10.2.1 serial port control register (spct, offset 80h) the serial port control register controls both the transmit and receive sections of the serial port. the format of the serial port control register is shown in figure 10-1. figure 10-1 serial port control register (spct, offset 80h) the value of spct at reset is 0000h. bits 15C12: reserved set to 0. bit 11: transmit holding register empty interrupt enable (txie) this bit enables the serial port to generate an interrupt for the transmit holding register empty condition, indicating that the serial port is ready to accept a new character for transmission. if this bit is 1 and the serial port transmit holding register does not contain valid data, the serial port generates an interrupt request. the value of txie after power-on reset is 0. bit 10: receive data ready interrupt enable (rxie) this bit enables the serial port to generate an interrupt for the receive data ready condition. if this bit is 1 and the serial port receive buffer register contains data that has been received on the serial port, the serial port generates an interrupt request. the value of rxie after power-on reset is 0. bit 9: loopback (loop) setting this bit to 1 places the serial port in the loopback mode. in this mode, the txd output is set high and the transmit shift register is connected to the receive shift register. data transmitted by the transmit section is immediately received by the receive section. the loopback mode is provided for testing the serial port. the value of loop after power-on reset is 0. bit 8: send break (brk) setting this bit to 1 causes the serial port to send a continuous level on the txd output. a break is a continuous low on the txd output for a duration of more than one frame transmission time. the level driven on the txd output is determined by the brkval bit. to use the transmitter to time the frame, set the brk bit when the transmitter is empty (indicated by the temt bit of the serial port status register), write the serial port transmit holding register, then wait until the temt bit is again set before resetting the brk bit. since the txd output is held constant while brk is set, the data written to the transmit holding register will not appear on the pin. the value of brk after power-on reset is 0. bit 7: break value (brkval) this bit determines the output value transmitted on the txd pin during a send break operation. if brkval is 1, a continuous high level is driven on the txd output. if brkval is 0, a continuous low level is driven on the txd output. only a continuous low value (brkval=0) will result in a break being detected by the receiver. the value of brkval after power-on reset is 0. 15 70 reserved txie rxie loop brk pmode brkval rmode rsie tmode stp wlgn
asynchronous serial port 10-3 bits 6C5: parity mode (pmode) this field specifies how parity generation and checking are performed during transmission and reception, as shown in table 10-2. table 10-2 parity mode bit settings if parity checking and generation is selected, a parity bit is received or sent in addition to the specified number of data bits. the value of pmode after power-on reset is 00b. bit 4: word length (wlgn) this bit determines the number of bits transmitted or received in a frame. if wlgn is 0, the serial port sends and receives 7 bits of data per frame. if wlgn is 1, the serial port sends and receives 8 bits of data per frame. the value of wlgn after power-on reset is 0. bit 3: stop bits (stp) a 0 in the stp bit specifies that one stop bit is used to signify the end of a frame. a 1 in this bit specifies that two stop bits are used to signify the end of a frame. the value of stp after power-on reset is 0. bit 2: transmit mode (tmode) the tmode bit enables data transmission and controls the operational mode of the serial port for the transmission of data. if tmode is 0, the transmit section and transmit interrupts of the serial port are disabled. if tmode is 1, the transmit section of the serial port is enabled. the value of tmode after power-on reset is 0. bit 1: receive status interrupt enable (rsie) this bit enables the serial port to generate an interrupt because of an exception during reception. if this bit is 1 and the serial port receives a break, or experiences a framing error, parity error, or overrun error, the serial port generates a serial port interrupt. the value of rsie after power-on reset is 0. bit 0: receive mode (rmode) this field enables data reception and controls the operational mode of the serial port for the reception of data. if rmode is 0, the receive section and receive interrupts of the serial port are disabled. if rmode is 1, the receive section of the serial port is enabled. the value of rmode after power-on reset is 0. parity pmode none (no parity bit in frame) 0 x odd (odd number of 1s in frame) 1 0 even (even number of 1s in frame) 1 1
asynchronous serial port 10-4 10.2.2 serial port status register (spsts, offset 82h) the serial port status register indicates the status of the transmit and receive sections of the serial port. the format of the serial port status register is shown in figure 10-2. figure 10-2 serial port status register (spsts, offset 82h) bits 15C7: reserved set to 0. bit 6: transmitter empty (temt) the temt bit is 1 when the transmitter has no data to transmit and the transmit shift register is empty. this indicates to software that it is safe to disable the transmit section. this bit is read-only. bit 5: transmit holding register empty (thre) when the thre bit is 1, the transmit holding register contains invalid data and can be written with data to be transmitted. when the thre bit is 0, the transmit holding register cannot be written because it contains valid data that has not yet been copied to the transmit shift register for transmission. if transmit interrupts are enabled by the tmode and txie fields, a serial port interrupt request is generated when the thre bit is 1. the thre bit is reset automatically by writing the transmit holding register. this bit is read-only, allowing other bits of the serial port status register to be written (i.e., resetting the brki bit) without interfering with the current data request. bit 4: receive data ready (rdr) when the rdr bit is 1, the receive buffer register contains data that can be read. when the rdr bit is 0, the receive buffer register does not contain valid data. this bit is read-only. if receive interrupts are enabled by the rmode and rxie fields, a serial port interrupt request is generated when the thre bit is 1. reading the receive buffer register resets the rdr bit. bit 3: break interrupt (brki) the brki bit is set to indicate that a break has been received. if the rsie bit is 1, the brki bit being set causes a serial port interrupt request. the brki bit should be reset by software. bit 2: framing error (fer) the fer bit is set to indicate that a framing error occurred during reception of data. if the rsie bit is 1, the fer bit being set causes a serial port interrupt request. the fer bit should be reset by software. bit 1: parity error (per) the per bit is set to indicate that a parity error occurred during reception of data. if the rsie bit is 1, the per bit being set causes a serial port interrupt request. the per bit should be reset by software. bit 0: overrun error (oer) the oer bit is set when an overrun error occurs during reception of data. if the rsie bit is 1, the oer bit being set causes a serial port interrupt request. the oer bit should be reset by software. 15 70 reserved temt thre rdr brki oer per fer
asynchronous serial port 10-5 10.2.3 serial port transmit data register (sptd, offset 84h) software writes this register (figure 10-4) with data to be transmitted on the serial port. the transmitter is double-buffered, and the transmit section copies data from the transmit data register to the transmit shift register (which is not accessible to software) before transmitting the data. figure 10-3 serial port transmit data register (sptd, offset 84h) the value of sptd at reset is undefined. bits 15C8: reserved bit 7C0: transmit data (tdata) this field is written with data to be transmitted on the serial port. the thre bit in the serial port status register indicates whether there is valid data in the sptd register. to avoid overwriting data in the sptd register, the thre bit should be read as a 1 before writing this register. writing this register causes the thre bit to be reset. 15 70 reserved tdata
asynchronous serial port 10-6 10.2.4 serial port receive data register (sprd, offset 86h) this register (figure 10-4) contains data received over the serial port. the receiver is double-buffered, and the receive section can be receiving a subsequent frame of data in the receive shift register (which is not accessible to software) while the receive data register is being read by software. figure 10-4 serial port receive data register (sprd, offset 86h) the value of sprd at reset is undefined. bits 15C8: reserved bits 7C0: receive data (rdata) this field contains data received on the serial port. the rdr bit of the serial port status register indicates valid data in the sprd register. to avoid reading invalid data, the rdr bit should be read as a 1 before the sprd register is read. reading this register causes the rdr bit to be reset. 15 70 reserved rdata
asynchronous serial port 10-7 10.2.5 serial port baud rate divisor register (spbaud, offset 88h) this register (figure 10-5) specifies a clock divisor for the generation of the serial clock that controls the serial port. the serial clock rate is 16 times the baud rate of transmission or reception of data. the spbaud register specifies the number of internal processor cycles in one phase (half period) of the 16x serial clock. if power-save mode is in effect, the baud rate divisor must be reprogrammed to reflect the new processor clock frequency. a general formula for the baud rate divisor is: bauddiv=(processor frequency ? (32 baud rate))C1 the maximum baud rate is 1/32 of the internal processor clock and is achieved by setting bauddiv=0000h. for a 40-mhz clock, a baud rate of 9600 can be achieved with bauddiv=129 (81h). a 1% error applies. figure 10-5 serial port baud rate divisor register (spbaud, offset 88h) the value of spbaud at reset is undefined. bits 15C0: baud rate divisor (bauddiv) this field specifies the divisor for the internal processor clock that generates one phase (half period) of the serial clock. the serial clock operates at 16 times the data transmission or reception baud rate. table 10-3 shows baud rate divisors for a range of common baud rates and processor clock rates. table 10-3 serial port baud rate table baud rate divisor based on cpu clock rate 20 mhz 25 mhz 33 mhz 40 mhz 300 2082 2603 3471 4165 600 1040 1301 1735 2082 1200 519 650 867 1040 2400 259 324 433 519 4800 129 161 216 259 9600 64 80 107 129 14,400 42 53 71 85 19,200 31 39 53 64 625 kbaud 0 n/a n/a 1 781.25 kbaud n/a 0 n/a n/a 1.041 mbaud n/a n/a 0 n/a 1.25 mbaud n/a n/a n/a 0 15 70 bauddiv
asynchronous serial port 10-8
synchronous serial interface 11-1 chapter 11 synchronous serial interface 11.1 overview the synchronous serial interface lets the am186em and am188em microcontrollers communicate with application-specific integrated circuits (asics) that require programmability but are short on pins. the four-pin interface permits half-duplex, bidirectional data transfer at speeds of up to 20 mbit/s with a 40-mhz cpu clock. unlike the asynchronous serial port, the ssi operates in a master/slave configuration. the am186em and am188em microcontrollers operate as the master port. the ssi interface provides four pins for communicating with system components: two enables (sden0 and sden1), a clock (sclk), and a data pin (sdata). five registers (see table 11-1) are used to control and monitor the interface. n the synchronous serial status register (sss) reports the current port status. n the synchronous serial control register (ssc) sets the port clock rate and controls the enable signals. n there are two data transmit registersthe synchronous serial transmit 0 register (ssd0) and the synchronous serial transmit 1 register (ssd1)but data is transmitted and received over a single pin (sdata). n the synchronous serial receive register (ssr) holds data received over the ssi. table 11-1 synchronous serial interface register summary offset from pcb register mnemonic register name 10h sss synchronous serial status 12h ssc synchronous serial control 14h ssd1 synchronous serial transmit 1 16h ssd0 synchronous serial transmit 0 18h ssr synchronous serial receive
synchronous serial interface 11-2 11.1.1 four-pin interface the sden1Csden0 enable pins can be enabled for up to two peripheral devices. transmit and receive operations are synchronized between the master (am186em or am188em microcontroller) and slave (peripheral) by means of the sclk output. sclk is derived from the processor internal clock divided by 2, 4, 8, or 16, as specified by the ssc register. sclk is only driven during data transmit or receive operations. the inactive state of sclk is high. if power-save mode is in effect, the sclk frequency is affected by the reduced processor clock frequency. data is transferred across the sdata input/output pin. data is driven on the falling edge of sclk and latched on the rising edge of sclk. the least-significant bit of the data is shifted first for both transmit and receive operations. during write operations, the processor holds data for one-half of an sclk period following the transfer of the last data bit. sdata has a weak keeper that holds the last value of sdata on the pin. 11.2 programmable registers the registers documented on the following pages are accessible to the system programmer.
synchronous serial interface 11-3 11.2.1 synchronous serial status register (sss, offset 10h) this read-only register indicates the state of the ssi port. the format of the synchronous serial status register is shown in figure 11-1. figure 11-1 synchronous serial status register (sss, offset 10h) the value of the sss register at reset is 0000h. bits 15C3: reserved set to 0. bit 2: receive/transmit error detect (re/te) this bit is set when the ssi detects either a read of the synchronous serial receive register or a write to one of the transmit registers while the ssi is busy (pb=1). this bit is reset when the sden output is inactive (bits de1C de0 in the ssc register are both 0). bit 1: data receive/transmit complete (dr/dt) the dr/dt bit is set at the end of the transfer of data bit 7 (sclk rising edge) during a transmit or receive operation. this bit is reset when the ssr register is read, when one of the ssd0 or ssd1 registers is written, when the sss register is read (unless the ssi completes an operation and sets the bit in the same cycle), or when both sden0 and sden1 become inactive. bit 0: ssi port busy (pb) when the pb bit is set, a transmit or receive operation is in progress. when pb is reset, the port is ready to transmit or receive data. 15 70 reserved re/te dr/dt pb
synchronous serial interface 11-4 11.2.2 synchronous serial control register (ssc, offset 12h) this read/write register controls the operation of the sden0Csden1 outputs and the transfer rate of the ssi port. the sden0 and sden1 outputs are asserted when a 1 is written to the corresponding bit. however, in the case when both de0 and de1 are set, only sden0 will be asserted. the format of the synchronous serial control register is shown in figure 11-2. figure 11-2 synchronous serial control register (ssc, offset 12h) the value of the ssc register at reset is 0000h. bits 15C6: reserved set to 1. bits 5C4: sclk divide (sclkdiv) these bits determine the sclk frequency. sclk is derived from the internal processor clock by dividing by 2, 4, 8, or 16. table 11-2 shows the processor clock frequency divider values for the possible sclkdiv settings. if power-save mode is in effect, the sclk frequency is affected by the reduced processor clock frequency. table 11-2 sclk divider values bits 3C2: reserved set to 0. bit 1: sden1 enable (de1) when this bit is set to 1, the sden1 pin is held high. when de1 is set to 0, the sden1 pin is low. bit 0: sden0 enable (de0) when this bit is set to 1, the sden0 pin is held high. when de0 is set to 0, the sden0 pin is low. sclkdiv sclk frequency divider 00b processor clock / 2 01b processor clock / 4 10b processor clock / 8 11b processor clock / 16 15 70 reserved sclkdiv de1 de0 res
synchronous serial interface 11-5 11.2.3 synchronous serial transmit 1 register (ssd1, offset 14h) synchronous serial transmit 0 register (ssd0, offset 16h) the synchronous serial transmit 1 and 0 registers contain data to be transferred from the processor to the peripheral on a write operation. only the least-significant 8 bits of the register are used. the format of ssd1 and ssd0 is shown in figure 11-3. writes to ssd1 or ssd0 cause the pb bit in the sss register to be set and a transmission sequence to begin as shown in figure 11-5 on page 11-8. a write to either ssd1 or ssd0 while the port is busy sets the re/te (receive/transmit error) bit in the sss register and does not generate additional data transfers. figure 11-3 synchronous serial transmit register (ssd1, ssd0, offsets 14h and 16h) the value of these registers at reset is undefined. bits 15C8: reserved set to 0. bits 7C0: send data (sd) data to transmit over the sdata pin. bit 0 is transmitted first, bit 7 is transmitted last. 15 70 reserved sd
synchronous serial interface 11-6 11.2.4 synchronous serial receive register (ssr, offset 18h) the synchronous serial receive (ssr) register contains the data transferred from the peripheral to the processor on a read operation. only the least-significant 8 bits of the register are used. the format of the ssr register is shown in figure 11-4. a receive data transmission is initiated by reading the ssr register while the port is not busy (pb bit in sss register is 0) and one or both of the enable bits (de1Cde0 in the ssc register) is set. a receive transmission is not initiated by reading the ssr register when neither of the enable bits is set (de1Cde0 = 00b). this allows the software to read the received data without initiating another receive transmission. a read of the synchronous serial receive register while the port is busy (pb bit is set in the sss register) sets the re/te (receive/transmit error) bit in the sss register and returns an indeterminate value. such a read does not generate additional data transfers. figure 11-4 synchronous serial receive register (ssr, offset 18h) the value of this register at reset is undefined. bits 15C8: reserved set to 0. bits 7C0: receive data (sr) data received over the sdata pin. bit 0 is transmitted first, bit 7 is transmitted last. 15 70 reserved sr
synchronous serial interface 11-7 11.3 ssi programming the ssi interface allows for a variety of software and hardware protocols. n signaling a read/write in general, software uses the first write to the ssi to transmit an address or count to the peripheral. this value can include a read/write flag in the case where the device supports both reads and writes. n using ssd1 as an address register the ssd1 register can be an address register that holds the value of the last address accessed, and the ssd0 register can be the data transmit register. in this case, the current value in the ssd1 register can be used by software to generate the next address or to determine if the last transaction was a read or a write. n using ssd1 and ssd0 as transmit registers for two peripheral devices in some systems, it may clarify the code and aid in debugging to view the two data transmit registers as unique to different peripheral devices. this allows the last value transmitted to each device to be examined by debug code.
synchronous serial interface 11-8 figure 11-5 synchronous serial interface multiple write figure 11-6 synchronous serial interface multiple read sclk sden sdata write to ssc bit de=1 write to ssd poll sss for pb=0 write to ssd poll sss for pb=0 write to ssd write to ssc bit de=0 poll sss for pb=0 pb=0 dr/dt=0 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=0 dr/dt=0 sclk sden sdata write to ssc bit de=1 write to ssd poll sss for pb=0 read from ssr (dummy) poll sss for pb=0 read from ssr write to ssc bit de=0 poll sss for pb=0 pb=0 dr/dt=0 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=0 dr/dt=0 read from ssr
programmable i/o pins 12-1 chapter 12 programmable i/o pins 12.1 overview thirty-two pins on the am186em and am188em microcontrollers are available as user- programmable i/o signals (pios). each of these pins can be used as a pio if the normal function of the pin is not needed. if a pin is enabled to function as a pio signal, the normal function is disabled and does not affect the pin. a pio signal can be configured to operate as an input or output with or without internal pullup or pulldown resistors, or as an open- drain output. after power-on reset, the pio pins default to various configurations. the column titled power-on reset state in table 12-1 lists the defaults for the pios. the system initialization code must reconfigure pios as required. the a19Ca17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address ffff0h. the dt/r , den , and srdy pins also default to normal operation on power-on reset. figure 12-1 programmable i/o pin operation vcc pin d 40 mhz (clk) oe rd pdata normal function 0 1 pio mode pio direction q int. bus q d mode dir. wr pdata piotri piopull data in piodrv normal data in
programmable i/o pins 12-2 table 12-1 pio pin assignments notes: 1. these pins are used by emulators. (emulators also use s 2Cs 0 , res , nmi, clkouta, bhe , ale, ad15Cad0, and a16Ca0.) 2. these pins revert to normal operation if bhe /aden (am186em) or rfsh 2/aden (am188em) is held low during power-on reset. 3. when used as a pio, input with pullup option available. 4. when used as a pio, input with pulldown option available. pio no. associated pin power-on reset status 0 tmrin1 input with pullup 1 tmrout1 input with pulldown 2 pcs 6/a2 input with pullup 3 pcs 5/a1 input with pullup 4 dt/r normal operation (3 ) 5 den normal operation (3 ) 6 srdy normal operation (4 ) 7 (1) a17 normal operation (3) 8 (1) a18 normal operation (3) 9 (1) a19 normal operation (3) 10 tmrout0 input with pulldown 11 tmrin0 input with pullup 12 drq0 input with pullup 13 drq1 input with pullup 14 mcs 0 input with pullup 15 mcs 1 input with pullup 16 pcs 0 input with pullup 17 pcs 1 input with pullup 18 pcs 2 input with pullup 19 pcs 3 input with pullup 20 sclk input with pullup 21 sdata input with pullup 22 sden0 input with pulldown 23 sden1 input with pulldown 24 mcs 2 input with pullup 25 mcs 3/rfsh input with pullup 26 (1,2) uzi input with pullup 27 txd input with pullup 28 rxd input with pullup 29 (1,2) s6/clkdiv 2 input with pullup 30 int4 input with pullup 31 int2 input with pullup
programmable i/o pins 12-3 12.2 pio mode registers table 12-2 shows the possible settings for the pio mode and pio direction bits. the am186em and am188em microcontrollers default the 32 pio pins to either 00b (normal operation) or 01b (pio input with weak internal pullup or pulldown enabled). pins that default to active high outputs at reset are pulled down. all other pins are pulled up or are normal operation. see table 12-2. the column titled power-on reset state in table 12-1 lists the defaults for the pios. the internal pullup resistor has a value of approximately 10 kohms. the internal pulldown resistor has a value of approximately 10 kohms. table 12-2 pio mode and pio direction settings 12.2.1 pio mode 1 register (piomode1, offset 76h) the value of piomode1 at reset is 0000h. bits 15C0: pio mode bits (pmode31Cpmode16) this field with the pio direction registers determines whether each pio pin performs its pre-assigned function or is enabled as a custom pio signal. the most significant bit of the pmode field determines whether pio31 is enabled, the next bit determines whether pio30 is enabled, and so on. table 12-2 shows the values that the pio mode bits and the pio direction bits can encode. 12.2.2 pio mode 0 register (piomode0, offset 70h) the value of piomode0 at reset is 0000h. bits 15C0: pio mode bits (pmode15Cpmode0) this field is a continuation of the pmode field in the pio mode 1 register. pio mode pio direction pin function 0 0 normal operation 0 1 pio input with pullup/pulldown 1 0 pio output 1 1 pio input without pullup/pulldown 15 7 0 pmode (31C16) 15 7 0 pmode (15C0) figure 12-3 pio mode 0 register (piomode0, offset 70h) figure 12-2 pio mode 1 register (piomode1, offset 76h)
programmable i/o pins 12-4 12.3 pio direction registers each pio is individually programmed as an input or output by a bit in one of the pio direction registers (see figure 12-4 and figure 12-5). table 12-2 on page 12-3 shows the values that the pio mode bits and the pio direction bits can encode. the column titled power-on reset state in table 12-1 lists the reset default values for the pios. bits in the pio direction registers have the same correspondence to pins as bits in the pio mode registers. 12.3.1 pio direction 1 register (pdir1, offset 78h) the value of pdir1 at reset is ffffh. bits 15C0: pio direction bits (pdir31Cpdir16) this field determines whether each pio pin acts as an input or an output. the most significant bit of the pdir field determines the direction of pio31, the next bit determines the direction of pio30, and so on. a 1 in the bit configures the pio signal as an input, and a 0 in the bit configures it as an output or as normal pin function. 12.3.2 pio direction 0 register (pdir0, offset 72h) the value of pdir0 at reset is fc0fh. bits 15C0: pio direction bits (pdir15Cpdir0) this field is a continuation of the pdir field in the pio direction 1 register. 15 7 0 pdir (31C16) figure 12-4 pio direction 1 register (pdir1, offset 78h) 15 7 0 pdir (15C0) figure 12-5 pio direction 0 register (pdir0, offset 72h)
programmable i/o pins 12-5 12.4 pio data registers if a pio pin is enabled as an output, the value in the corresponding bit in one of the pio data registers (see figure 12-6 and figure 12-7) is driven on the pin with no inversion (low=0, high=1). if a pio pin is enabled as an input, the value on the pio pin is reflected in the value of the corresponding bit in the pio data register, with no inversion. bits in the pio data registers have the same correspondence to pins as bits in the pio mode registers and pio direction registers. 12.4.1 pio data register 1 (pdata1, offset 7ah) bits 7C0: pio data bits (pdata31Cpdata16) this field determines the level driven on each pio pin or reflects the external level of the pin, depending upon whether the pin is configured as an output or an input in the pio direction registers. the most significant bit of the pdata field indicates the level of pio31, the next bit indicates the level of pio30, and so on. the value of pdata1 at reset is undefined. 12.4.2 pio data register 0 (pdata0, offset 74h) bits 15C0: pio data bits (pdata15Cpdata0) this field is a continuation of the pdata field in the pio data 1 register. the value of pdata0 at reset is undefined. 12.5 open-drain outputs the pio data registers permit the pio signals to be operated as open-drain outputs. this is accomplished by keeping the appropriate pdata bits constant in the pio data register and writing the data value into its associated bit position in the pio direction register, so the output is either driving low or is disabled, depending on the data. pdata (15C0) 15 7 0 figure 12-6 pio data 1 register (pdata1, offset 7ah) 15 7 0 pdata (31C16) figure 12-7 pio data 0 register (pdata0, offset 74h)
programmable i/o pins 12-6
register summary a-1 appendix a register summary this appendix summarizes the peripheral control block registers. table a-1 lists all the registers. figure a-1 shows the layout of each of the internal registers. the column titled comment in table a-1 is used to identify the specific use of interrupt registers when there is a mix of master mode and slave mode usage. the registers that are marked as slave & master can have different configurations for the different modes.
register summary a-2 table a-1 internal register summary hex offset mnemonic register description comment fe relreg peripheral control block relocation register f6 rescon reset configuration register f4 prl processor release level register f0 pdcon power-save control register e4 edram enable rcu register e2 cdram clock prescaler register e0 mdram memory partition register d8 d1tc dma 1 transfer count register d6 d1dsth dma 1 destination address high register d4 d1dstl dma 1 destination address low register d2 d1srch dma 1 source address high register d0 d1srcl dma 1 source address low register ca d0con dma 0 control register c8 d0tc dma 0 transfer count register c6 d0dsth dma 0 destination address high register c4 d0dstl dma 0 destination address low register c2 d0srch dma 0 source address high register c0 d0srcl dma 0 source address low register a8 mpcs pcs and mcs auxiliary register a6 mmcs midrange memory chip select register a4 pacs peripheral chip select register a2 lmcs low memory chip select register a0 umcs upper memory chip select register 88 spbaud serial port baud rate divisor register 86 sprd serial port receive data register 84 sptd serial port transmit data register 82 spsts serial port status register 80 spct serial port control register 7a pdata1 pio data 1 register 78 pdir1 pio direction 1 register 76 piomode1 pio mode 1 register 74 pdata0 pio data 0 register 72 pdir0 pio direction 0 register 70 piomode0 pio mode 0 register 66 t2con timer 2 mode/control register 62 t2cmpa timer 2 maxcount compare a register 60 t2cnt timer 2 count register 5e t1con timer 1 mode/control register
register summary a-3 table a-1 internal register summary (continued) hex offset mnemonic register description comment 5c t1cmpb timer 1 maxcount compare b register 5a t1cmpa timer 1 maxcount compare a register 58 t1cnt timer 1 count register 56 t0con timer 0 mode/control register 54 t0cmpb timer 0 maxcount compare b register 52 t0cmpa timer 0 maxcount compare a register 50 t0cnt timer 0 count register 44 spicon serial port interrupt control register master mode 42 wdcon watchdog timer interrupt control register master mode 40 i4con int4 control register master mode 3e i3con int3 control register master mode 3c i2con int2 control register master mode 3a i1con int1 control register master mode t2intcon timer 2 interrupt control register slave mode 38 i0con int0 control register master mode t1intcon timer 1 interrupt control register slave mode 36 dma1con dma 1 interrupt control register slave & master 34 dma0con dma 0 interrupt control register slave & master 32 tcucon timer interrupt control register master mode t0intcon timer 0 interrupt control register slave mode 30 intsts interrupt status register slave & master 2e reqst interrupt request register slave & master 2c inserv in-service register slave & master 2a primsk priority mask register slave & master 28 imask interrupt mask register slave & master 26 pollst poll status register master mode 24 poll poll register master mode 22 eoi end-of-interrupt register master mode eoi specific end-of-interrupt register slave mode 20 intvec interrupt vector register slave mode 18 ssr synchronous serial receive register 16 ssd0 synchronous serial transmit 0 register 14 ssd1 synchronous serial transmit 1 register 12 ssc synchronous serial control register 10 sss synchronous serial status register
register summary a-4 figure a-1 internal register summary 15 7 0 res s/m r19Cr8 res m/io peripheral control block relocation register (relreg) page 4-4 offset (hexadecimal) fe reset configuration register (rescon) page 4-5 f6 15 7 0 rc processor release level register (prl) page 4-6 f4 15 7 0 prl reserved caf cad 15 7 0 cbd power-save control register (pdcon) page 4-7 f2Cf0 psen f0 000 0000 0 cbf 15 70 00 000 t8Ct0 0 e enable rcu register (edram) page 6-2 e4 15 70 00 000 0 rc8Crc0 0 clock prescaler register (cdram) page 6-2 e2
register summary a-5 figure a-1 internal register summary (continued) 15 7 0 m6Cm0 ra19 ra13 0 memory partition register (mdram) page 6-1 e0 15 7 0 tc15Ctc0 dma 1 transfer count register (d1tc) page 9-5 d8 15 7 0 dda15Cdda0 dma 1 destination address low register (d1dstl) page 9-7 d4 15 70 reserved dsa19Cdsa16 dma 1 source address high register (d1srch) page 9-8 d2 15 70 dsa15Cdsa0 dma 1 source address low register (d1srcl) page 9-9 d0 15 7 0 reserved dda19Cdda16 dma 1 destination address high register (d1dsth) page 9-6 d6 15 7 0 dinc ddec sm/io sinc sdec b /w st chg res tc int syn p tdrq dma 1 control register (d1con) page 9-3 ca dm/io 00000000
register summary a-6 figure a-1 internal register summary (continued) 15 7 0 dinc ddec sm/io sinc sdec b /w st chg res tc int syn p tdrq dma 0 control register (d0con) page 9-3 ca dm/io 15 7 0 tc15Ctc0 dma 0 transfer count register (d0tc) page 9-5 c8 15 7 0 reserved dda19Cdda16 dma 0 destination address high register (d0dsth) page 9-6 c6 15 7 0 dda15Cdda0 dma 0 destination address low register (d0dstl) page 9-7 c4 15 70 reserved dsa19Cdsa16 dma 0 source address high register (d0srch) page 9-8 c2 15 70 dsa15Cdsa0 dma 0 source address low register (d0srcl) page 9-9 c0
register summary a-7 figure a-1 internal register summary (continued) 15 7 0 ms ex m6Cm0 1111r1Cr0 pcs and mcs auxiliary register (mpcs) page 5-10 a8 r2 15 7 0 ba19Cba13 1 1 1 r1Cr0 11 1 a6 midrange memory chip select register (mmcs) page 5-8 r2 15 70 ba19Cba11 1 1 r3 r1Cr0 1 peripheral chip select register (pacs) page 5-12 a4 r2 15 7 0 r1Cr0 0 ub2Cub0 1 1 1 1 r7 pse 1 1 1 a19 low memory chip select register (lmcs) page 5-6 a2 r2 r2 15 7 0 lb2Clb0 10000r7 r1Cr0 0 a19 111 upper memory chip select register (umcs) page 5-4 a0 serial port baud rate divisor register (spbaud) page 10-7 88 15 7 0 bauddiv
register summary a-8 figure a-1 internal register summary (continued) serial port receive data register (sprd) page 10-6 86 15 7 0 reserved rdata serial port transmit data register (sptd) page 10-5 84 15 70 reserved tdata serial port status register (spsts) page 10-4 82 15 7 0 reserved temt thre rdr brki oer per fer serial port control register (spct) page 10-2 80 15 7 0 reserved txie rxie loop brk pmode brkval rmode rsie tmode stp wlgn pio data 1 register (pdata1) page 12-5 7a 15 7 0 pdata31Cpdata16 pio direction 1 register (pdir1) page 12-4 78 15 7 0 pdir31Cpdir16
register summary a-9 figure a-1 internal register summary (continued) pio mode 1 register (piomode1) page 12-3 76 15 7 0 pmode31Cpmode16 pio data 0 register (pdata0) page 12-5 74 pdata15Cpdata0 15 7 0 pio direction 0 register (pdir0) page 12-4 72 15 7 0 pdir15Cpdir0 pio mode 0 register (piomode0) page 12-3 70 15 7 0 pmode15Cpmode0 15 70 en int inh 0mc cont 00000 000 0 0 66 timer 2 mode/control register (t2con) page 8-5 15 70 tc15Ctc0 62 timer 2 maxcount compare a register (t2cmpa) page 8-7
register summary a-10 figure a-1 internal register summary (continued) 15 70 tc15Ctc0 60 timer 2 count register (t2cnt) page 8-6 15 7 0 en int inh riu 0 p ext mc rtg alt cont 00000 5e timer 1 mode/control register (t1con) page 8-3 15 7 0 tc15Ctc0 5c timer 1 maxcount compare b register (t1cmpb) page 8-7 15 70 tc15Ctc0 5a timer 1 maxcount compare a register (t1cmpa) page 8-7 15 70 tc15Ctc0 58 timer 1 count register (t1cnt) page 8-6 15 70 en int inh riu 0 p ext mc rtg alt cont 00000 56 timer 0 mode/control register (t0con) page 8-3 15 70 tc15Ctc0 54 timer 0 maxcount compare b register (t0cmpb) page 8-7
register summary a-11 figure a-1 internal register summary (continued) 15 7 0 tc15Ctc0 52 timer 0 maxcount compare a register (t0cmpa) page 8-7 15 70 tc15Ctc0 50 timer 0 count register (t0cnt) page 8-6 serial port interrupt control register (spicon) master mode page 7-19 44 15 70 msk res pr2Cpr0 reserved (1) watchdog timer interrupt control register (wdcon) master mode page 7-18 42 15 70 reserved msk pr2Cpr0 15 7 0 msk ltm pr2Cpr0 int4 control register (i4con) master mode page 7-15 reserved 40 15 70 reserved pr2Cpr0 msk ltm int3 control register (i3con) 3e master mode page 7-15
register summary a-12 figure a-1 internal register summary (continued) 15 70 reserved pr2Cpr0 msk ltm int2 control register (i2con) 3c master mode page 7-15 15 70 reserved msk ltm c sfnm int1 control register (i1con) 3a master mode page 7-13 pr2Cpr0 msk 15 70 pr2Cpr0 timer 2 interrupt control register (t2intcon) 3a slave mode page 7-29 reserved 15 70 reserved msk ltm c sfnm int0 control register (i0con) 38 master mode page 7-13 pr2Cpr0 msk 15 70 pr2Cpr0 timer 1 interrupt control register (t1intcon) 38 slave mode page 7-29 reserved 15 70 pr2Cpr0 msk dma 1 interrupt control register (dma1con) 36 master modepage 7-17 slave modepage 7-29 reserved
register summary a-13 figure a-1 internal register summary (continued) 15 70 pr2Cpr0 msk dma 0 interrupt control register (dma0con) 34 master modepage 7-17 slave modepage 7-29 reserved 15 70 pr2Cpr0 msk 32 timer interrupt control register (tcucon) master modepage 7-17 timer 0 interrupt control register (t0intcon) slave modepage 7-29 reserved 15 70 reserved tmr2Ctmr0 dhlt interrupt status register (intsts) 30 master modepage 7-20 slave modepage 7-30 interrupt request register (reqst) 2e 15 70 reserved res tmr d0 d1 i0 i1 i2 i3 i4 wd spi master mode page 7-21 15 70 reserved d0 d1 tmr1 tmr2 res tmr0 interrupt request register (reqst) 2e slave mode page 7-31
register summary a-14 figure a-1 internal register summary (continued) in-service register (inserv) 2c 15 70 reserved res tmr d0 d1 i0 i1 i2 i3 i4 wd spi master mode page 7-22 15 70 reserved d0 d1 tmr1 tmr2 res tmr0 in-service register (inserv) 2c slave mode page 7-32 2a master modepage 7-23 slave modepage 7-33 15 70 reserved prm2Cprm0 priority mask register (primsk) interrupt mask register (imask) 28 15 70 reserved res tmr d0 d1 i0 i1 i2 i3 i4 wd spi master mode page 7-24 15 70 reserved d0 d1 tmr1 tmr2 res tmr0 interrupt mask register (imask) 28 slave mode page 7-34
register summary a-15 figure a-1 internal register summary (continued) 15 70 s4Cs0 ireq poll status register (pollst) 26 master mode page 7-25 reserved 15 70 s4Cs0 ireq poll register (poll) 24 master mode page 7-26 reserved 15 70 s4Cs0 nspec end-of-interrupt register (eoi) 22 master mode page 7-27 reserved 15 70 l2Cl0 specific end-of-interrupt register (eoi) 22 slave mode page 7-35 reserved 15 70 00 0 t4Ct0 interrupt vector register (intvec) 20 slave mode page 7-36 reserved
register summary a-16 figure a-1 internal register summary (continued) synchronous serial receive register (ssr) page 11-6 18 15 70 reserved sr synchronous serial transmit 0 register (ssd0) page 11-5 16 15 70 reserved sd synchronous serial transmit 1 register (ssd1) page 11-5 14 15 7 0 reserved sd synchronous serial control register (ssc) page 11-4 12 15 70 reserved sclkdiv de1 de0 res synchronous serial status register (sss) page 11-3 10 15 7 0 reserved re/te dr/dt pb
index i-1 index symbols (iret) interrupt return 7-4 a a1 signal (latched address bit 1) definition 3-8 a19-a0 signals (address bus) definition 3-1 a2 signal (latched address bit 2) definition 3-8 ad15-ad0 signals (address and data bus) definition 3-2 ad7-ad0 signals (address and data bus) definition 3-1 ale signal (address latch enable) definition 3-2 alt bit (alternate compare bit) timer 0 mode/control register 8-4 timer 1 mode/control register 8-4 am186em microcontroller design philosophy xiii product support iii am188em microcontroller signal descriptions ad7-ad0 (address and data bus) 3-1 ma15-ma7 (multiplexed address bus) 3-2 rfsh2/aden (refresh 2/address enable) 3-11 wb (write byte) 3-14 ardy signal (asynchronous ready) definition 3-2 b b/w bit (byte/word select) 9-4 ba19-ba11 field (base address) peripheral chip select register 5-12 ba19-ba13 field (base address) midrange memory chip select register 5-8 bauddiv field (baud rate divisor) 10-7 bhe signal (bus high enable) definition 3-3 bits alt (alternate compare bit) 8-4 b/w (byte/word select) 9-4 ba19-ba11 (base address) 5-12 ba19-ba13 (base address) 5-8 bauddiv (baud rate divisor) 10-7 brk (send break) 10-2 brki (break interrupt) 10-4 brkval (break value) 10-2 c (cascade mode) 7-13 cad (clkouta drive disable) 4-7 caf (clkouta output frequency) 4-7 cbd (clkoutb drive disable) 4-7 cbf (clkoutb output frequency) 4-7 chg (change start bit) 9-4 cont (continuous mode bit) 8-4, 8-5 d1-d0 (dma channel interrupt inservice) 7-22, 7- 32, 7-34 d1-d0 (dma channel interrupt masks) 7-24 d1-d0 (dma channel interrupt request) 7-21, 7-31 dda15-dda0 (dma destination address low) 9-7 dda19-dda16 (dma destination address high) 9- 6 ddec (destination decrement) 9-3 de0 (sden0 enable) 11-4 de1 (sden1 enable) 11-4 dhlt (dma halt) 7-20, 7-30 dinc (destination increment) 9-3 dm/io (destination address space select) 9-3 dr/dt (data receive/transmit complete) 11-3 dsa15-dsa0 (dma source address low) 9-9 dsa19-dsa16 (dma source address high) 9-8 e (enable rcu) 6-2 en (enable bit) 8-3, 8-5 ex (pin selector) 5-11 ext (external clock bit) 8-4 f2-f0 (clock divisor select) 4-7
index i-2 fer (framing error) 10-4 i4-i0 (interrupt inservice) 7-22 i4-i0 (interrupt mask) 7-24 i4-i0 (interrupt requests) 7-21 inh (inhibit bit) 8-3, 8-5 int (interrupt bit) 8-3, 8-5 int (interrupt) 9-4 ireq (interrupt request) 7-25, 7-26 l2-l0 (interrupt type) 7-35 lb2-lb0 (lower boundary) 5-4 loop (loopback) 10-2 ltm (leveltriggered mode) 7-13, 7-15, 7-16 m/io (memory/i/o space) 4-4 m6-m0 (mcs block size) 5-10 m6-m0 (refresh base) 6-1 mc (maximum count bit) 8-3, 8-5 ms (memory/i/o space selector) 5-11 msk (interrupt mask) 7-17 msk (mask) 7-13, 7-15, 7-16, 7-18, 7-19, 7-29 nspec (nonspecific eoi) 7-27 oer (overrun error) 10-4 p (prescaler bit) 8-3 p (relative priority) 9-4 pb (ssi port busy) 11-3 pdata15-pdata0 (pio data bits) 12-5 pdata31-pdata16 (pio data bits) 12-5 pdir15-pdir0 (pio direction bits) 12-4 pdir31-pdir16 (pio direction bits) 12-4 per (parity error) 10-4 pmode (parity mode) 10-3 pmode15-pmode0 (pio mode bits) 12-3 pmode31-pmode16 (pio mode bits) 12-3 pr2-pr0 (priority level) 7-29 pr2-pr0 (priority) 7-13, 7-15, 7-16, 7-17, 7-18, 7- 19 prm2-prm0 (priority field mask) 7-23, 7-33 pse (psram mode enable) 5-7 psen (enable powersave mode) 4-7 r19-r8 (relocation address bits) 4-4 r1-r0 (wait state value) 5-5, 5-7, 5-9, 5-11 r2 (ready mode) 5-5, 5-7, 5-9, 5-11 r7 (address disable) 5-5, 5-7 rc (reset configuration) 4-5 rc8-rc0 (refresh counter reload value) 6-2 rdata (receive data) 10-6 rdr (receive data ready) 10-4 re/te (receive/transmit error detect) 11-3 riu (register in use) 8-3 rmode (receive mode) 10-3 rsie (receive status interrupt enable) 10-3 rtg (retrigger bit) 8-3 rxie (receive data ready interrupt enable) 10-2 s/m (slave/master) 4-4 s4-s0 (poll status) 7-25, 7-26 s4-s0 (source vector type) 7-27 sd (send data) 11-5 sdec (source decrement) 9-4 sfnm (special fully nested mode) 7-13 sinc (source increment) 9-4 sm/io (source address space select) 9-3 spi (serial port interrupt inservice) 7-22 spi (serial port interrupt mask) 7-24 spi (serial port interrupt request) 7-21 sr (receive data) 11-6 st (start/stop dma channel) 9-4 stp (stop bits) 10-3 syn1-syn0 (synchronization type) 9-4 t4-t0 (interrupt type) 7-36 t8-t0 (refresh count) 6-2 tc (terminal count) 9-4 tc15-tc0 (timer compare value) 8-7 tc15-tc0 (timer count register) 9-5 tc15-tc0 (timer count value) 8-6 tdata (transmit data) 10-5 tdrq (timer enable/disable request) 9-4 temt (transmitter empty) 10-4 thre (transmit holding register empty) 10-4 tmode (transmit mode) 10-3 tmr (timer interrupt inservice) 7-22 tmr (timer interrupt mask) 7-24 tmr (timer interrupt request) 7-21 tmr0 (timer 0 interrupt inservice) 7-32 tmr0 (timer 0 interrupt mask) 7-34 tmr0 (timer 0 interrupt request) 7-31 tmr2-tmr0 (timer interrupt request) 7-20, 7-30 tmr2-tmr1 (timer 2/timer 1 interrupt inservice) 7-32 tmr2-tmr1 (timer 2/timer 1 interrupt mask) 7-34 trm2-tmr1 (timer2/timer1 interrupt request) 7- 31 txie (transmit holding register empty interrupt enable) 10-2 ub2-ub0 (upper boundary) 5-6
index i-3 wd (virtual watchdog timer interrupt inservice) 7- 22 wd (virtual watchdog timer interrupt mask) 7-24 wd (virtual watchdog timer interrupt request) 7- 21 wlgn (word length) 10-3 brk bit (send break) 10-2 brki bit (break interrupt) 10-4 brkval bit (break value) 10-2 c c bit (cascade mode) 7-13 cad bit (clkouta drive disable) 4-7 caf bit (clkouta output frequency) 4-7 cascade mode 7-10 cbd bit (clkoutb drive disable) 4-7 cbf bit (clkoutb output frequency) 4-7 chg bit (change start bit) 9-4 clkdiv2 signal (clock divide by 2) definition 3-12 clkouta signal (clock output a) definition 3-3 clkoutb signal (clock output b) definition 3-4 clock prescaler register description 6-2 cont bit (continuous mode bit) timer 0 mode/control register 8-4 timer 1 mode/control register 8-4 timer 2 mode/control register 8-5 d d1-d0 field (dma channel interrupt inservice) 7-22, 7- 32, 7-34 d1-d0 field (dma channel interrupt masks) 7-24 d1-d0 field (dma channel interrupt request) 7-21, 7- 31 dda15-dda0 field (dma destination address low) 9-7 dda19-dda16 field (dma destination address high) 9-6 ddec bit (destination decrement) 9-3 de0 bit (sden0 enable) 11-4 de1 bit (sden1 enable) 11-4 den signal (data enable) definition 3-4 development tools thirdparty products xiv dhlt bit (dma halt) 7-20, 7-30 dinc bit (destination increment) 9-3 dm/io bit (destination address space select) 9-3 dma 0 control register description 9-3 dma 0 destination address high register description 9-6 dma 0 destination address low register description 9-7 dma 0 interrupt control register description master mode 7-17 slave mode 7-29 dma 0 source address high register description 9-8 dma 0 source address low register description 9-9 dma 0 transfer count register description 9-5 dma 1 control register description 9-3 dma 1 destination address high register description 9-6 dma 1 destination address low register description 9-7 dma 1 interrupt control register description master mode 7-17 slave mode 7-29 dma 1 source address high register description 9-8 dma 1 source address low register description 9-9 dma 1 transfer count register description 9-5 documentation amd e86 family publications xiv ordering documentation and literature iii dr/dt bit (data receive/transmit complete) 11-3 drq1-drq0 signals (dma requests) definition 3-4 dsa15-dsa0 field (dma source address low) 9-9 dsa19-dsa16 field (dma source address high) 9-8 dt/r signal (data transmit or receive) definition 3-4
index i-4 e e bit (enable rcu) 6-2 en bit (enable bit) timer 0 mode/control register 8-3 timer 1 mode/control register 8-3 timer 2 mode/control register 8-5 en bit (enable powersave mode) 4-7 enable rcu register description 6-2 endofinterrupt processing 7-11 endofinterrupt register description master mode 7-27 eoi 7-11 ex bit (pin selector) 5-11 ext bit (external clock bit) timer 0 mode/control register 8-4 timer 1 mode/control register 8-4 external interrupt acknowledge bus cycles table 7-7 f f2-f0 field (clock divisor select) 4-7 fer bit (framing error) 10-4 figure external interrupt acknowledge bus cycles 7-7 fully nested mode interrupt controller connections 7-9 fully nested mode 7-9 fully nested mode interrupt controller connections 7-9 h hlda signal (bus hold acknowledge) definition 3-4 hold signal (bus hold request) definition 3-4 i i4-i0 field (interrupt inservice) 7-22 i4-i0 field (interrupt mask) 7-24 i4-i0 field (interrupt requests) 7-21 if (the interrupt enable flag) 7-2 inh bit (inhibit bit) timer 0 mode/control register 8-3 timer 1 mode/control register 8-3 timer 2 mode/control register 8-5 inservice register description master mode 7-22 slave mode 7-32 instruction exceptions 7-3 int bit (interrupt bit) timer 0 mode/control register 8-3 timer 1 mode/control register 8-3 timer 2 mode/control register 8-5 int0 control register description master mode 7-13 int0 signal (maskable interrupt request 0) definition 3-5 int1 control register description master mode 7-13 int1 signal (maskable interrupt request 1) definition 3-5 int2 control register description master mode 7-15 int2 signal (maskable interrupt request 2) definition 3-5 int3 control register description master mode 7-15 int3 signal (maskable interrupt request 3) definition 3-6 int4 control register description master mode 7-16 int4 signal (maskable interrupt request 4) definition 3-6 inta0 signal (interrupt acknowledge 0) definition 3-5 inta1 signal (interrupt acknowledge 1) definition 3-6 interrupt acknowledge 7-7 interrupt conditions and sequence 7-4 interrupt control unit 7-1 interrupt controller registers master mode 7-12 slave mode 7-28 interrupt controller reset conditions 7-8 interrupt enable flag (if) 7-2
index i-5 interrupt mask bit 7-2 interrupt mask register description master mode 7-24 slave mode 7-34 interrupt priority 7-2, 7-5 interrupt request register description master mode 7-21 slave mode 7-31 interrupt return (iret) 7-4 interrupt status register description master mode 7-20 slave mode 7-30 interrupt type 7-1 interrupt types 7-6 interrupt types table 7-3 interrupt vector register description slave mode 7-36 interrupt vector table 7-2 interrupts array bounds exception 7-6 breakpoint 7-6 cascade mode 7-10 divide error exception 7-6 eoi 7-11 esc opcode exception 7-6 fully nested mode 7-9 instruction exceptions 7-3 into overflow detected 7-6 maskable and nonmaskable 7-2 master mode operation 7-9 nonmaskable (nmi) 7-6 polled 7-11 slave mode 7-28 slave mode nesting 7-28 special fully nested mode 7-11 trace 7-6 unused opcode 7-6 ireq bit (interrupt request) poll register 7-26 poll status register 7-25 irq signal (slave interrupt request) definition 3-6 l l2-l0 field (interrupt type) 7-35 lb2-lb0 field (lower boundary) 5-4 lcs signal (lower memory chip select) definition 3-6 loop bit (loopback) 10-2 low memory chip select register description 5-6 ltm bit (leveltriggered mode) int0 control register 7-13 int1 control register 7-13 int2 control register 7-15 int3 control register 7-15 int4 control register 7-16 m m/io bit (memory/i/o space) 4-4 m6-m0 field (mcs block size) 5-10 m6-m0 field (refresh base) 6-1 ma15-ma7 signals (multiplexed address bus) definition 3-2 maskable interrupts 7-2 master mode interrupt registers 7-12 master mode operation 7-9 mc bit (maximum count bit) timer 0 mode/control register 8-3 timer 1 mode/control register 8-3 timer 2 mode/control register 8-5 mcs2-mcs0 signals (midrange memory chip selects 2-0) definition 3-7 mcs3 signal (midrange memory chip select 3) definition 3-7 memory partition register description 6-1 midrange memory chip select register description 5-8 ms bit (memory/i/o space selector) 5-11 msk (interrupt mask bit) 7-2 msk bit (interrupt mask) dma interrupt control registers 7-17 timer interrupt control registers 7-17 msk bit (mask) dma interrupt control registers 7-29 int0 control register 7-13
index i-6 int1 control register 7-13 int2 control register 7-15 int3 control register 7-15 int4 control register 7-16 serial port interrupt control register 7-19 timer interrupt control registers 7-29 virtual watchdog timer interrupt control register 7-18 n nmi signal (nonmaskable interrupt) definition 3-7 nonmaskable interrupts 7-2, 7-6 nspec bit (nonspecific eoi) 7-27 o oer bit (overrun error) 10-4 once0 signal (once mode request 0) definition 3-6 once1 signal (once mode request 1) definition 3-13 p p bit (prescaler bit) timer 0 mode/control register 8-3 timer 1 mode/control register 8-3 p bit (relative priority) 9-4 pb bit (ssi port busy) 11-3 pcs and mcs auxiliary register description 5-10 pcs3-pcs0 signals (peripheral chip selects 3-0) definition 3-7 pcs5 signal (peripheral chip select 5) definition 3-8 pcs6 signal (peripheral chip select 6) definition 3-8 pdata15-pdata0 field (pio data bits) 12-5 pdata31-pdata16 field (pio data bits) 12-5 pdir15-pdir0 field (pio direction bits) 12-4 pdir31-pdir16 field (pio direction bits) 12-4 per bit (parity error) 10-4 peripheral chip select register description 5-12 peripheral control block relocation register 4-4 physical dimensions xiv pin description xiv pio data 0 register description 12-5 pio data 1 register description 12-5 pio direction 0 register description 12-4 pio direction 1 register description 12-4 pio mode 0 register description 12-3 pio mode 1 register description 12-3 pio31-pio0 signals (programmable i/o pins 31-0) definition 3-8 pllbyps signal (pll bypass) definition 3-14 pmode field (parity mode) 10-3 pmode15-pmode0 field (pio mode bits) 12-3 pmode31-pmode16 field (pio mode bits) 12-3 poll register description master mode 7-26 poll status register description master mode 7-25 polled interrupts 7-11 powersave control register description 4-7 pr2-pr0 field (priority level) dma interrupt control register 7-29 timer interrupt control register 7-29 pr2-pr0 field (priority) dma interrupt control registers 7-17 int0 control register 7-13 int1 control register 7-13 int2 control register 7-15 int3 control register 7-15 int4 control register 7-16 serial port interrupt control register 7-19 timer interrupt control registers 7-17 virtual watchdog timer interrupt control register 7-18 priority mask register description master mode 7-23
index i-7 slave mode 7-33 prm2-prm0 field (priority field mask) 7-23, 7-33 processor release level register description 4-6 product support bulletin board service iii documentation and literature iii technical support hotline iii pse bit (psram mode enable) 5-7 r r19-r8 field (relocation address bits) 4-4 r1-r0 field (wait state value) low memory chip select register 5-7 midrange memory chip select register 5-9 pcs and mcs auxiliary register 5-11 upper memory chip select register 5-5 r2 bit (ready mode) low memory chip select register 5-7 midrange memory chip select register 5-9 pcs and mcs auxiliary register 5-11 upper memory chip select register 5-5 r7 field (address disable) upper memory chip select register 5-5, 5-7 rc field (reset configuration) 4-5 rc8-rc0 field (refresh counter reload value) 6-2 rd signal (read strobe) definition 3-11 rdata field (receive data) 10-6 rdr bit (receive data ready) 10-4 re/te bit (receive/transmit error detect) 11-3 registers clock prescaler (cdram, offset e2h) 6-2 dma 0 control (d0con, offset cah) 9-3 dma 0 interrupt control (dma0con, offset 34h) 7- 17, 7-29 dma 0 source address high (d0srch, offset c2h) 9-8 dma 0 source address low (d0srcl, offset c0h) 9-9 dma 0 transfer count (d0tc, offset c8h) 9-5 dma 1 control (d1con, offset dah) 9-3 dma 1 destination address high (d0dsth, offset c6h) 9-6 dma 1 destination address high (d1dsth, offset d6h) 9-6 dma 1 destination address low (d0dstl, offset c4h) 9-7 dma 1 destination address low (d1dstl, offset d4h) 9-7 dma 1 interrupt control (dma1con, offset 36h) 7- 17, 7-29 dma 1 source address high (d1srch, offset d2h) 9-8 dma 1 source address low (d1srcl, offset d0h) 9-9 dma 1 transfer count (d1tc, offset d8h) 9-5 enable rcu (edram, offset e4h) 6-2 endofinterrupt (eoi, offset 22h) 7-27 inservice (inserv, offset 2ch) 7-22, 7-32 int0 control (int0, offset 38h) master mode 7-13 int1 control (int1, offset 3ah) master mode 7-13 int2 control (int2, offset 3ch) master mode 7-15 int3 control (int3, offset 3eh) master mode 7-15 int4 control (int4, offset 40h) master mode 7-16 interrupt mask (imask, offset 28h) 7-24, 7-34 interrupt request (reqst, offset 2eh) 7-21, 7-31 interrupt status (insts, offset 30h) 7-20 interrupt status (intsts, offset 30h) 7-30 interrupt vector (intvec, offset 20h) 7-36 low memory chip select (lmcs, offset a2h) 5-6 memory partition (mdram, offset e0h) 6-1 midrange memory chip select (mmcs, offset a6h) 5-8 pcs and mcs auxiliary (mpcs, offset a8h) 5-10 peripheral chip select (pacs, offset a4h) 5-12 peripheral control block relocation (relreg, off- set feh) 4-4 pio data 0 (pdata0, offset 74h) 12-5 pio data 1 (pdata1, offset 7ah) 12-5 pio direction 0 (pdir0, offset 72h) 12-4 pio direction 1 (pdir1, offset 78h) 12-4 pio mode 0 (piomode0, offset 70h) 12-3 pio mode 1 (piomode1, offset 76h) 12-3 poll (poll, offset 24h) 7-26 poll status (pollst, offset 26h) 7-25 powersave control (pdcon, offset f0h) 4-7 priority mask (primsk, offset 2ah) 7-23, 7-33 processor release level (prl, offset f4) 4-6 reset configuration (rescon, offset f6h) 4-5
index i-8 serial port baud rate divisor (spbaud, offset 88h) 10-7 serial port control (spct, offset 80h) 10-2 serial port interrupt control (spicon, offset 44h) master mode 7-19 serial port receive data (sprd, offset 86h) 10-6 serial port status (spsts, offset 82h) 10-4 serial port transmit (sptd, offset 84h) 10-5 specific endofinterrupt (eoi, offset 22h) 7-35 synchronous serial control (ssc, offset 12h) 11-4 synchronous serial receive (ssr, offset 18h) 11- 6 synchronous serial status (sss, offset 10h) 11-3 synchronous serial transmit 0 (ssd0, offset 14h) 11-5 synchronous serial transmit 1 (ssd1, offset 14h) 11-5 timer 0 count (t0cnt, offset 50h) 8-6 timer 0 interrupt control (t0intcon, offset 32h) 7-29 timer 0 maxcount compare a (t0cmpa, offset 52h) 8-7 timer 0 maxcount compare b (t0cmpb, offset 54h) 8-7 timer 0 mode and control (t0con, offset 56h) 8-3 timer 1 count (t1cnt, offset 58h) 8-6 timer 1 interrupt control (t1intcon, offset 38h) 7-29 timer 1 maxcount compare a (t1cmpa, offset 5ah) 8-7 timer 1 maxcount compare b (t1cmpb, offset 5ch) 8-7 timer 1 mode and control (t1con, offset 5eh) 8-3 timer 2 count (t2cnt, offset 60h) 8-6 timer 2 interrupt control (t2intcon, offset 3ah) 7-29 timer 2 maxcount compare a (t2cmpa, offset 62h) 8-7 timer 2 mode and control (t2con, offset 66h) 8-5 timer interrupt control (tcucon, offset 32h) 7-17 upper memory chip select (umcs, offset a0h) 5-4 watchdog timer interrupt control (wdcon, offset 42h) master mode 7-18 res signal (reset) definition 3-11 reset interrupt controller conditions 7-8 reset configuration register description 4-5 rfsh signal (automatic refresh) definition 3-7 rfsh2/aden signal definition 3-11 riu bit (register in use) timer 0 mode/control register 8-3 timer 1 mode/control register 8-3 rmode bit (receive mode) 10-3 rsie bit (receive status interrupt enable) 10-3 rtg bit (retrigger bit) timer 0 mode/control register 8-3 timer 1 mode/control register 8-3 rxd signal (receive data) definition 3-11 rxie bit (receive data ready interrupt enable) 10-2 s s/m bit (slave/master) 4-4 s2-s0 signals (bus cycle status 2-0) definition 3-11 s4-s0 field (poll status) poll register 7-26 poll status register 7-25 s4-s0 field (source vector type) 7-27 s6 signal (bus cycle status 6) definition 3-12 sclk signal (serial clock) definition 3-12 sd field (send data) 11-5 sdata signal (serial data) definition 3-12 sdec bit (source decrement) 9-4 sden1-sden0 signals (serial data enables 1-0) definition 3-12 select signal (slave select) definition 3-5 serial port baud rate divisor register description 10-7 serial port control register description 10-2 serial port interrupt control register description master mode 7-19 serial port receive data register description 10-6
index i-9 serial port status register description 10-4 serial port transmit data register description 10-5 sfnm bit (special fully nested mode) 7-13 signal description a1 (latched address bit 1) 3-8 a19-a0 (address bus) 3-1 a2 (latched address bit 2) 3-8 ad15-ad0 (address and data bus) 3-2 ad7-ad0 (address and data bus) 3-1 ale (address latch enable) 3-2 ardy (asynchronous ready) 3-2 bhe (bus high enable) 3-3 clkdiv2 (clock divide by 2) 3-12 clkouta (clock output a) 3-3 clkoutb (clock output b) 3-4 den (data enable) 3-4 drq1-drq0 (dma requests) 3-4 dt/r (data transmit or receive) 3-4 hlda (bus hold acknowledge) 3-4 hold (bus hold request) 3-4 int0 (maskable interrupt request 0) 3-5 int1 (maskable interrupt request 1) 3-5 int2 (maskable interrupt request 2) 3-5 int3 (maskable interrupt request 3) 3-6 int4 (maskable interrupt request 4) 3-6 inta0 (interrupt acknowledge 0) 3-5 inta1 (interrupt acknowledge 1) 3-6 irq (slave interrupt request) 3-6 lcs (lower memory chip select) 3-6 ma15-ma7 (multiplexed address bus) 3-2 mcs2-mcs0 (midrange memory chip selects 2-0) 3-7 mcs3 (midrange memory chip select 3) 3-7 nmi (nonmaskable interrupt) 3-7 once0 (once mode request 0) 3-6 once1 (once mode request 1) 3-13 pcs30-pcs0 (peripheral chip selects 3-0) 3-7 pcs5 (peripheral chip select 5) 3-8 pcs6 (peripheral chip select 6) 3-8 pio31-pio0 (programmable i/o pins 31-0) 3-8 pllbyps (pll bypass) 3-14 rd (read strobe) 3-11 res (reset) 3-11 rfsh (automatic refresh) 3-7 rfsh2/aden (refresh 2/address enable) 3-11 rxd (receive data) 3-11 s2-s0 (bus cycle status 2-0) 3-11 s6 (bus cycle status 6) 3-12 sclk (serial clock) 3-12 sdata (serial data) 3-12 sden1-sden0 (serial data enables 1-0) 3-12 select (slave select) 3-5 srdy (synchronous ready) 3-13 tmrin0 (timer input 0) 3-13 tmrin1 (timer input 1) 3-13 tmrout0 (timer output 0) 3-13 tmrout1 (timer output 1) 3-13 txd (transmit data) 3-13 ucs (upper memory chip select) 3-13 uzi (upper zero indicate) 3-14 wb (write byte) 3-14 whb (write high byte) 3-14 wlb (write low byte) 3-14 wr (write strobe) 3-14 sinc bit (source increment) 9-4 slave mode interrupts 7-28 slave mode nesting 7-28 sm/io bit (source address space select) 9-3 software interrupt 7-3 special fully nested mode 7-11 specific endofinterrupt register description slave mode 7-35 spi bit (serial port interrupt inservice) 7-22 spi bit (serial port interrupt mask) 7-24 spi bit (serial port interrupt request) 7-21 sr field (receive data) 11-6 srdy signal (synchronous ready) definition 3-13 st bit (start/stop dma channel) 9-4 stp bit (stop bits) 10-3 syn1-syn0 field (synchronization type) 9-4 synchronous serial control register description 11-4 synchronous serial receive register description 11-6 synchronous serial status register description 11-3 synchronous serial transmit 0 register description 11-5
index i-10 synchronous serial transmit 1 register description 11-5 t t4-t0 field (interrupt type) 7-36 t8-t0 field (refresh count) 6-2 table interrupt controller registers in master mode 7-12 interrupt controller registers in slave mode 7-28 interrupt types 7-3 tc bit (terminal count) 9-4 tc15-tc0 field (timer compare value) 8-7 tc15-tc0 field (timer count register) 9-5 tc15-tc0 field (timer count value) 8-6 tdata field (transmit data) 10-5 tdrq bit (timer enable/disable request) 9-4 temt bit (transmitter empty) 10-4 thermal characteristics xiv thre bit (transmit holding register empty) 10-4 timer 0 count register description 8-6 timer 0 interrupt control register description slave mode 7-29 timer 0 maxcount compare a register description 8-7 timer 0 maxcount compare b register description 8-7 timer 0 mode and control register description 8-3 timer 1 count register description 8-6 timer 1 interrupt control register description slave mode 7-29 timer 1 maxcount compare a register description 8-7 timer 1 maxcount compare b register description 8-7 timer 1 mode and control register description 8-3 timer 2 count register description 8-6 timer 2 interrupt control register description slave mode 7-29 timer 2 maxcount compare b register description 8-7 timer 2 mode and control register description 8-5 timer interrupt control register description master mode 7-17 timing characteristics xiv tmode bit (transmit mode) 10-3 tmr bit (timer interrupt inservice) 7-22 tmr bit (timer interrupt mask) 7-24 tmr bit (timer interrupt request) 7-21 tmr0 bit (timer 0 interrupt inservice) 7-32 tmr0 bit (timer 0 interrupt mask) 7-34 tmr0 bit (timer 0 interrupt request) 7-31 tmr2-tmr0 field (timer interrupt request) 7-20, 7-30 tmr2-tmr1 field (timer 2/timer 1 interrupt inservice) 7-32 tmr2-tmr1 field (timer 2/timer 1 interrupt mask) 7- 34 tmrin0 signal (timer input 0) definition 3-13 tmrin1 signal (timer input 1) definition 3-13 tmrout0 signal (timer output 0) definition 3-13 tmrout1 signal (timer output 1) definition 3-13 trace interrupt 7-6 trm2-tmr1 field (timer2/timer1 interrupt request) 7- 31 txd signal (transmit data) definition 3-13 txie bit (transmit holding register empty interrupt en- able) 10-2 u ub2-ub0 field (upper boundary) 5-6 ucs signal (upper memory chip select) definition 3-13 upper memory chip select register description 5-4 uzi signal (upper zero indicate) definition 3-14
index i-11 w watchdog timer interrupt control register description master mode 7-18 wb signal (write byte) definition 3-14 wd bit (virtual watchdog timer interrupt inservice) 7- 22 wd bit (virtual watchdog timer interrupt mask) 7-24 wd bit (virtual watchdog timer interrupt request) 7-21 whb signal (write high byte) definition 3-14 wlb signal (write low byte) definition 3-14 wlgn bit (word length) 10-3 wr signal (write strobe) definition 3-14
index i-12

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